SBOS966H april   2019  – june 2023 TLV9061-Q1 , TLV9062-Q1 , TLV9064-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Comparison Table
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information: TLV9061-Q1
    5. 8.5 Thermal Information: TLV9062-Q1
    6. 8.6 Thermal Information: TLV9064-Q1
    7. 8.7 Electrical Characteristics
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Rail-to-Rail Input
      2. 9.3.2 Rail-to-Rail Output
      3. 9.3.3 Overload Recovery
      4. 9.3.4 Shutdown Function
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Typical Low-Side Current Sense Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Typical Comparator Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Input and ESD Protection
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.8 Typical Characteristics

at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)

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Figure 8-1 Offset Voltage Production Distribution
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Figure 8-3 Offset Voltage vs Temperature
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VS = 1.8 V to 5.5 V
Figure 8-5 Offset Voltage vs Power Supply
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RL = 2 kΩ
Figure 8-7 Open-Loop Gain vs Temperature
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Figure 8-9 Input Bias Current vs Temperature
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Figure 8-11 CMRR and PSRR vs Frequency (Referred to Input)
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VCM = (V–) – 0.1 V to (V+) – 1.4 V
TA= –40°C to 125°CRL= 10 kΩVS = 5.5 V
Figure 8-13 CMRR vs Temperature
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VS = 1.8 V to 5.5 V
Figure 8-15 0.1-Hz to 10-Hz Input Voltage Noise
GUID-8ADA2980-82AC-4815-B3CD-6F5CAF2F48E9-low.png
VS = 5.5 VVCM = 2.5 VRL = 2 kΩ
VOUT = 0.5 VRMSBW = 80 kHzG = +1
Figure 8-17 THD + N vs Frequency
GUID-6E20BE0D-496D-4559-9574-AFC1F138FBBB-low.png
VS = 5.5 VVCM = 2.5 VRL = 2 kΩ
G = –1BW = 80 kHzf = 1 kHz
Figure 8-19 THD + N vs Amplitude
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Figure 8-21 Quiescent Current vs Temperature
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V+ = 2.75 VV– = –2.75 VG = +1 V/V
VOUT step = 100 mVp-pRL = 10 kΩ
Figure 8-23 Small-Signal Overshoot vs Load Capacitance
GUID-DA7E9BA1-3040-4BBB-8767-D7644DB83073-low.png
V+ = 2.75 VV– = –2.75 V
Figure 8-25 No Phase Reversal
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V+ = 2.75 VV– = –2.75 VG = 1 V/V
 
Figure 8-27 Small-Signal Step Response
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Figure 8-29 Short-Circuit Current vs Temperature
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PRF = –10 dBm
Figure 8-31 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency
GUID-DF5EE675-389A-4738-AE7A-4A88BDCB7E60-low.png
VS = 5.5 V
Figure 8-33 Phase Margin vs Capacitive Load
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Figure 8-35 Large Signal Settling Time (Positive)
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TA = –40°C to 125°C
Figure 8-2 Offset Voltage Drift Distribution
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V+ = 2.75 V V– = –2.75 V
Figure 8-4 Offset Voltage vs Common-Mode Voltage
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CL = 10 pF
Figure 8-6 Open-Loop Gain and Phase vs Frequency
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Figure 8-8 Closed-Loop Gain vs Frequency
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V+ = 2.75 VV– = –2.75 V
Figure 8-10 Output Voltage Swing vs Output Current
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VS = 5.5 VVCM = –0.1 V to 5.6 VTA= –40°C to 125°C
RL= 10 kΩ
Figure 8-12 CMRR vs Temperature
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VS = 1.8 V to 5.5 V
 
Figure 8-14 PSRR vs Temperature
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Figure 8-16 Input Voltage Noise Spectral Density vs Frequency
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VS = 5.5 VRL = 2 kΩG = +1
VCM = 2.5 VBW = 80 kHzf = 1 kHz
Figure 8-18 THD + N vs Amplitude
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Figure 8-20 Quiescent Current vs Supply Voltage
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Figure 8-22 Open-Loop Output Impedance vs Frequency
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V+ = 2.75 VV– = –2.75 VG = –1 V/V
VOUT step = 100 mVp-pRL = 10 kΩ
Figure 8-24 Small-Signal Overshoot vs Load Capacitance
GUID-4A60E95F-0B82-441F-8D9E-A5EF51122E35-low.png
V+ = 2.75 VV– = –2.75 VG = –10 V/V
Figure 8-26 Overload Recovery
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V+ = 2.75 VV– = –2.75 VCL = 100 pF
G = 1 V/V
Figure 8-28 Large-Signal Step Response
GUID-530E0E01-27C5-41CF-BCC1-1BA382901D5F-low.png
RL = 10 k‎ΩCL = 10 pF
Figure 8-30 Maximum Output Voltage vs Frequency and Supply Voltage
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V+ = 2.75 VV– = –2.75 V
Figure 8-32 Channel Separation vs Frequency
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VS = 5.5 V
Figure 8-34 Open Loop Voltage Gain vs Output Voltage
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Figure 8-36 Large Signal Settling Time (Negative)