SBOSA23G May   2020  – March 2024 TLV9151-Q1 , TLV9152-Q1 , TLV9154-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 EMI Rejection
      2. 6.3.2 Thermal Protection
      3. 6.3.3 Capacitive Load and Stability
      4. 6.3.4 Common-Mode Voltage Range
      5. 6.3.5 Phase Reversal Protection
      6. 6.3.6 Electrical Overstress
      7. 6.3.7 Overload Recovery
      8. 6.3.8 Typical Specifications and Distributions
      9. 6.3.9 Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
        2. 8.1.1.2 TI Precision Designs
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5.     Trademarks
    6. 8.5 Electrostatic Discharge Caution
    7. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±125 ±895 µV
TA = –40°C to 125°C ±925
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±0.3 µV/℃
PSRR Input offset voltage versus power supply VCM = V–, VS = 4 V to 16 V TA = –40°C to 125°C ±0.3 ±1.5 μV/V
VCM = V–, VS = 2.7 V to 16 V(4) ±1 ±10.6
Channel separation f = 0 Hz 5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
TA = –40°C to 125°C(4) ±1 nA
IOS Input offset current ±10 pA
TA = –40°C to 125°C(4) ±1 nA
NOISE
EN Input voltage noise f = 0.1 Hz to 10 Hz   1.8 μVPP
  0.3   µVRMS
eN Input voltage noise density f = 1 kHz 10.8   nV/√Hz
f = 10 kHz   9.4  
iN Input current noise f = 1 kHz   2   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = 16 V, (V–) – 0.1 V < VCM < (V+) – 2 V (Main input pair) TA = –40°C to 125°C 99 130 dB
VS = 4 V, (V–) – 0.1 V < VCM < (V+) – 2 V (Main input pair) 82 100
VS = 2.7 V, (V–) – 0.1 V < VCM < (V+) – 2 V (Main input pair)(4) 75 95
VS = 2.7 V to 16 V, (V+) – 1 V < VCM < (V+) + 0.1 V (Aux input pair) 85
INPUT CAPACITANCE
ZID Differential 100 || 9 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 16 V, VCM = V–
(V–) + 0.1 V < VO < (V+) –  0.1 V		 120 145 dB
TA = –40°C to 125°C 142
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) –  0.1 V		 104 130
TA = –40°C to 125°C 125
VS = 2.7 V, VCM = V–
(V–) + 0.1 V < VO < (V+) –  0.1 V(4)		 101 120
TA = –40°C to 125°C 118
FREQUENCY RESPONSE
GBW Gain-bandwidth product 4.5 MHz
SR Slew rate VS = 16 V, G = +1, CL = 20 pF 21 V/μs
tS Settling time To 0.01%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF 2.5 μs
To 0.01%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF 1.5
To 0.1%, VS = 16 V, VSTEP = 10 V , G = +1, CL = 20 pF 2
To 0.1%, VS = 16 V, VSTEP = 2 V , G = +1, CL = 20 pF 1
Phase margin G = +1, RL = 10 kΩ 60 °
Overload recovery time VIN  × gain > VS 400 ns
THD+N Total harmonic distortion + noise (1) VS = 16 V, VO = 3 VRMS, G = 1, f = 1 kHz 0.00021%
OUTPUT
  Voltage output swing from rail (positive and negative) VS = 16 V, RL = no load   5 10 mV
TA = –40°C to 125°C(4) 15
VS = 16 V, RL = 10 kΩ   50 55
TA = –40°C to 125°C(4) 75
VS = 16 V, RL = 2 kΩ   200 250
TA = –40°C to 125°C(4) 350
VS = 2.7 V, RL = no load   1 6
TA = –40°C to 125°C(4) 10
VS = 2.7 V, RL = 10 kΩ   5 12
TA = –40°C to 125°C(4) 18
VS = 2.7 V, RL = 2 kΩ 25 40
TA = –40°C to 125°C(4)   60
ISC Short-circuit current ±75 mA
CLOAD Capacitive load drive 1000
 pF
ZO Open-loop output impedance f = 1 MHz, IO = 0 A 525 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 560 685 µA
IO = 0 A, (TLV9151-Q1) 560 691
IO = 0 A TA = –40°C to 125°C 750
IO = 0 A, (TLV9151-Q1) 769
SHUTDOWN
IQSD Quiescent current per amplifier VS = 2.7 V to 16 V, all amplifiers disabled, SHDN = V– 30 45 µA
ZSHDN Output impedance during shutdown VS = 2.7 V to 16 V, amplifier disabled 320 || 2 MΩ || pF
VIH Logic high threshold voltage (amplifier enabled) (V–) + 0.8V (V–) + 1.1V V
VIL Logic low threshold voltage (amplifier disabled) (V–) + 0.2V (V–) + 0.8V V
tON Amplifier enable time (full shutdown) (2) (3) G = +1, VCM = V-, VO = 0.1 × VS/2 8 µs
tON Amplifier enable time (partial shutdown) (2) (3) G = +1, VCM = V-, VO = 0.1 × VS/2 3
tOFF Amplifier disable time (2) VCM = V-, VO = VS/2 3 µs
SHDN pin input bias current (per pin) VS = 2.7 V to 16 V, (V+) ≥ SHDN ≥ (V–) + 0.9 V 500 nA
VS = 2.7 V to 16 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V 150
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
(2) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(3) Full shutdown refers to the dual TLVxx2S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad TLV9xx4S having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode, the internal biasing circuitry remains operational and the enable time is shorter.
(4) Specified by characterization only.