SBOSA71 July   2021 TMCS1107-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Typical Characteristics
      1. 7.10.1 Insulation Characteristics Curves
  8. 8 Parameter Measurement Information
    1. 8.1 Accuracy Parameters
      1. 8.1.1 Sensitivity Error
      2. 8.1.2 Offset Error and Offset Error Drift
      3. 8.1.3 Nonlinearity Error
      4. 8.1.4 Power Supply Rejection Ratio
      5. 8.1.5 Common-Mode Rejection Ratio
      6. 8.1.6 External Magnetic Field Errors
    2. 8.2 Transient Response Parameters
      1. 8.2.1 Slew Rate
      2. 8.2.2 Propagation Delay and Response Time
      3. 8.2.3 Current Overload Parameters
      4. 8.2.4 CMTI, Common-Mode Transient Immunity
    3. 8.3 Safe Operating Area
      1. 8.3.1 Continuous DC or Sinusoidal AC Current
      2. 8.3.2 Repetitive Pulsed Current SOA
      3. 8.3.3 Single Event Current Capability
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current Input
      2. 9.3.2 Input Isolation
      3. 9.3.3 High-Precision Signal Chain
        1. 9.3.3.1 Lifetime and Environmental Stability
        2. 9.3.3.2 Frequency Response
        3. 9.3.3.3 Transient Response
      4. 9.3.4 Internal Reference Voltage
      5. 9.3.5 Current-Sensing Measurable Ranges
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down Behavior
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Total Error Calculation Examples
        1. 10.1.1.1 Room Temperature Error Calculations
        2. 10.1.1.2 Full Temperature Range Error Calculations
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Insulation Specifications

PARAMETERTEST CONDITIONSVALUEUNIT
GENERAL
CLRExternal clearance(1)Shortest terminal-to-terminal distance through air4mm
CPGExternal creepage(1)Shortest terminal-to-terminal distance across the package surface4mm
DTIDistance through the insulationMinimum internal gap (internal clearance)60µm
CTIComparative tracking indexDIN EN 60112; IEC 60112>400V
Material groupII
Overvoltage categoryRated mains voltage ≤ 150 VRMSI-IV
Rated mains voltage ≤ 300 VRMSI-III
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)420VPK
VIOWMMaximum working isolation voltageAC voltage (sine wave); Time Dependent Dielectric Breakdown test, see 297VRMS
DC voltage420VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM = 4242VPK, t = 60 s (qualification);
VTEST = 1.2 × VIOTM = 5090VPK, t = 1 s (100% production)		4242VPK
VIOSMMaximum surge isolation voltage(2)Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800VPK (qualification)		6000VPK
qpdApparent charge(3)Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM = 4242VPK, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 700VPK, tm = 10 s		≤5pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM = 4242VPK, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 700VPK, tm = 10 s		≤5
Method b3: At routine test (100% production) and preconditioning (type test)
Vini = 1.2 × VIOTM = 5090VPK, tini = 1 s;
Vpd(m) = 1.2 × VIOTM = 5090VPK, tm = 1 s		≤5
CIOBarrier capacitance, input to output(4)VIO = 0.4 sin (2πft), f = 1 MHz0.6pF
RIOIsolation resistance, input to output(4)VIO = 500 V, TA = 25°C>1012Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C>1011Ω
VIO = 500 V at TS = 150°C>109Ω
Pollution degree2
UL 1577
VISOWithstand isolation voltageVTEST = VISO, t = 60 s (qualification); VTEST = 1.2 × VISO,
t = 1 s (100% production)		3000VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Take care to maintain the creepage and clearance distance of the board design to make sure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(3) Apparent charge is electrical discharge caused by a partial discharge (pd).
(4) All pins on each side of the barrier tied together creating a two-terminal device