SBOS702D October 2014 – December 2018 TMP102-Q1
Figure 13 shows the internal register structure of the TMP102-Q1 device. The 8-bit pointer register of the device is used to address a given data register. The pointer register uses the two least-significant bytes (LSBs) (see Table 13) to identify which of the data registers must respond to a read or write command. The power-up reset value of P1 and P0 is 00. By default, the TMP102-Q1 device reads the temperature on power up.
|0||0||Temperature register (read only)|
|0||1||Configuration register (read and write)|
|1||0||TLOW register (read and write)|
|1||1||THIGH register (read and write)|