SLOS887F September 2014 – June 2022 TMP112-Q1
PRODUCTION DATA
Figure 8-8 shows the internal register structure of the TMP112-Q1 device. The 8-bit pointer register of the device is used to address a given data register. The pointer register uses the two LSBs (see Table 8-12) to identify which of the data registers must respond to a read or write command. The power-up reset value of the P[1:0] byte is 00. By default, the TMP112-Q1 device reads the temperature on power up.
Table 8-6 lists the pointer address of the registers available in the TMP112-Q1 device.Table 8-7 lists the bits of the pointer register byte. During a write command, bytes P2 through P7 must always be 0.
P1 | P0 | REGISTER |
---|---|---|
0 | 0 | Temperature register (read only [R]) |
0 | 1 | Configuration register (read-write [R/W]) |
1 | 0 | T(LOW) register (R/W) |
1 | 1 | T(HIGH) register (R/W) |
P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | 0 | Register Bits |