SLOS887E September   2014  – December 2018 TMP112-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
    1.     Simplified Schematic
  3. Description
    1.     Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Specifications for User-Calibrated Systems
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Temperature Output
      2. 7.3.2 Serial Interface
        1. 7.3.2.1 Bus Overview
        2. 7.3.2.2 Serial Bus Address
        3. 7.3.2.3 Writing and Reading Operation
        4. 7.3.2.4 Slave Mode Operation
          1. 7.3.2.4.1 Slave Receiver Mode
          2. 7.3.2.4.2 Slave Transmitter Mode
        5. 7.3.2.5 SMBus Alert Function
        6. 7.3.2.6 General Call
        7. 7.3.2.7 High-Speed (Hs) Mode
        8. 7.3.2.8 Timeout Function
        9. 7.3.2.9 Timing Diagrams
          1. 7.3.2.9.1 Two-Wire Timing Diagrams
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuos-Conversion Mode
      2. 7.4.2 Extended Mode (EM)
      3. 7.4.3 Shutdown Mode (SD)
      4. 7.4.4 One-Shot and Conversion Ready Mode (OS)
      5. 7.4.5 Thermostat Mode (TM)
        1. 7.4.5.1 Comparator Mode (TM = 0)
        2. 7.4.5.2 Interrupt Mode (TM = 1)
    5. 7.5 Programming
      1. 7.5.1 Pointer Register
      2. 7.5.2 Temperature Register
      3. 7.5.3 Configuration Register
        1. 7.5.3.1 Shutdown Mode (SD)
        2. 7.5.3.2 Thermostat Mode (TM)
        3. 7.5.3.3 Polarity (POL)
        4. 7.5.3.4 Fault Queue (F1/F0)
        5. 7.5.3.5 Converter Resolution (R1 and R0)
        6. 7.5.3.6 One-Shot (OS)
        7. 7.5.3.7 Extended Mode (EM)
        8. 7.5.3.8 Alert (AL)
        9. 7.5.3.9 Conversion Rate (CR)
      4. 7.5.4 High- and Low-Limit Registers
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Calibrating for Improved Accuracy
        1. 8.1.1.1 Example 1: Finding Worst-Case Accuracy From –15°C to 50°C
        2. 8.1.1.2 Example 2: Finding Worst-Case Accuracy From 25°C to 100°C
      2. 8.1.2 Using The Slope Specifications With a 1-Point Calibration
        1. 8.1.2.1 Power Supply-Level Contribution to Accuracy
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pointer Register

Figure 15 shows the internal register structure of the TMP112-Q1 device. The 8-bit pointer register of the device is used to address a given data register. The pointer register uses the two LSBs (see Table 12) to identify which of the data registers must respond to a read or write command. The power-up reset value of the P[1:0] byte is 00. By default, the TMP112-Q1 device reads the temperature on power up.

TMP112-Q1 ai_internal_reg_bos397.gifFigure 15. Internal Register Structure

Table 6 lists the pointer address of the registers available in the TMP112-Q1 device.Table 7 lists the bits of the pointer register byte. During a write command, bytes P2 through P7 must always be 0.

Table 6. Pointer Addresses

P1 P0 REGISTER
0 0 Temperature register (read only [R])
0 1 Configuration register (read-write [R/W])
1 0 T(LOW) register (R/W)
1 1 T(HIGH) register (R/W)

Table 7. Pointer Register Byte

P7 P6 P5 P4 P3 P2 P1 P0
0 0 0 0 0 0 Register Bits