184.108.40.206 Timing Diagrams
The TMP112-Q1 device is two-wire, SMBus and I2C interface-compatible. Figure 10 to Figure 13 illustrate the various operations on the TMP112-Q1 device. Parameters for Figure 10 are listed in the Timing Requirements table. The bus definitions are defined as follows:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line, from high to low, when the SCL line is high, defines a START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. Using the TMP112-Q1 device for single byte updates is also possible. To update only the most-significant (MS) byte, terminate the communication by issuing a START or STOP communication on the bus.
Acknowledge:Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a not-acknowledge (1) on the last byte that has been transmitted by the slave.