SNIS214E june 2021 – july 2023 TMP114
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The TMP114 has a standard bidirectional I2C interface that is controlled by a controller device in order to be configured or read the status of this device. Each target on the I2C bus has a specific device address to differentiate between other target devices that are on the same I2C bus. Many target devices require configuration upon start-up to set the behavior of the device. This is typically done when the controller accesses internal register maps of the target, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. The TMP114 includes 50-ns glitch suppression filters, allowing the device to coexist on an I3C mixed bus. The TMP114 supports transmission data rates up to 1 MHz.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to a supply through a pullup resistor. The size of the pullup resistor is determined by the amount of capacitance on the I2C lines and the communication frequency. For further details, see the I2C Pullup Resistor Calculation application report. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition (see Figure 8-7 and Figure 8-8).
The following is the general procedure for a controller to access a target device: