SNIS214E june   2021  – july 2023 TMP114

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing
    7. 7.7 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 1.2 V Compatible Logic Inputs
      2. 8.3.2 Cyclic Redundancy Check (CRC)
      3. 8.3.3 Temperature Limits
      4. 8.3.4 Slew Rate Warning
      5. 8.3.5 NIST Traceability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conversion Mode
      2. 8.4.2 Shutdown Mode
        1. 8.4.2.1 One-Shot Temperature Conversions
    5. 8.5 Programming
      1. 8.5.1 Temperature Data Format
      2. 8.5.2 I2C and SMBus Interface
      3. 8.5.3 Device Address
      4. 8.5.4 Bus Transactions
        1. 8.5.4.1 Auto-Increment
        2. 8.5.4.2 Writes
          1. 8.5.4.2.1 CRC Enabled Writes
        3. 8.5.4.3 Reads
          1. 8.5.4.3.1 CRC Enabled Reads
        4. 8.5.4.4 General Call Reset Function
        5. 8.5.4.5 Time-Out Function
        6. 8.5.4.6 Coexist on I3C MixedBus
        7. 8.5.4.7 Cyclic Redundancy Check Implementation
    6. 8.6 Register Map
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Separate I2C Pullup and Supply Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Equal I2C Pullup and Supply Voltage Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YMT|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

I2C and SMBus Interface

The TMP114 has a standard bidirectional I2C interface that is controlled by a controller device in order to be configured or read the status of this device. Each target on the I2C bus has a specific device address to differentiate between other target devices that are on the same I2C bus. Many target devices require configuration upon start-up to set the behavior of the device. This is typically done when the controller accesses internal register maps of the target, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. The TMP114 includes 50-ns glitch suppression filters, allowing the device to coexist on an I3C mixed bus. The TMP114 supports transmission data rates up to 1 MHz.

The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to a supply through a pullup resistor. The size of the pullup resistor is determined by the amount of capacitance on the I2C lines and the communication frequency. For further details, see the I2C Pullup Resistor Calculation application report. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition (see Figure 8-7 and Figure 8-8).

The following is the general procedure for a controller to access a target device:

  1. If a controller wants to send data to a target:
    • Controller-transmitter sends a START condition and addresses the target-receiver.
    • Controller-transmitter sends the requested register to write target-receiver.
    • Controller-transmitter sends data to target-receiver.
    • Controller-transmitter terminates the transfer with a STOP condition.
  2. If a controller wants to receive or read data from a target:
    • Controller-receiver sends a START condition and addresses the target-transmitter.
    • Controller-receiver sends the requested register to read to target-transmitter.
    • Controller-receiver receives data from the target-transmitter.
    • Controller-receiver terminates the transfer with a STOP condition.
GUID-20200606-SS0I-PSHR-LTR6-GVPCZNW9PT9W-low.gif Figure 8-7 Definition of Start and Stop Conditions
GUID-20200606-SS0I-VK4C-HMNC-3T6ZLC5LM716-low.gif Figure 8-8 Bit Transfer