SNIS217C december   2020  – may 2023 TMP139

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down and Device Reset
      3. 7.3.3 Temperature Result and Limits
      4. 7.3.4 Bus Reset
      5. 7.3.5 Interrupt Generation
      6. 7.3.6 Parity Error Check
      7. 7.3.7 Packet Error Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Mode
      2. 7.4.2 Serial Address
      3. 7.4.3 I2C Mode Operation
        1. 7.4.3.1 Host I2C Write Operation
        2. 7.4.3.2 Host I2C Read Operation
        3. 7.4.3.3 Host I2C Read Operation in Default Read Address Pointer Mode
        4. 7.4.3.4 Switching from I2C Mode to I3C Basic Mode
      4. 7.4.4 I3C Basic Mode Operation
        1. 7.4.4.1 Host I3C Write Operation without PEC
        2. 7.4.4.2 Host I3C Write Operation with PEC
        3. 7.4.4.3 Host I3C Read Operation without PEC
        4. 7.4.4.4 Host I3C Read Operation with PEC
        5. 7.4.4.5 Host I3C Read Operation in Default Read Address Pointer Mode
      5. 7.4.5 In Band Interrupt
        1. 7.4.5.1 In Band Interrupt Arbitration Rules
        2. 7.4.5.2 In Band Interrupt Bus Transaction
      6. 7.4.6 Common Command Codes Support
        1. 7.4.6.1 ENEC CCC
        2. 7.4.6.2 DISEC CCC
        3. 7.4.6.3 RSTDAA CCC
        4. 7.4.6.4 SETAASA CCC
        5. 7.4.6.5 GETSTATUS CCC
        6. 7.4.6.6 DEVCAP CCC
        7. 7.4.6.7 SETHID CCC
        8. 7.4.6.8 DEVCTRL CCC
      7. 7.4.7 I/O Operation
      8. 7.4.8 Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1 Enabling Interrupt Mechanism
      2. 7.5.2 Clearing Interrupt
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Register Map

Table 7-11 TMP139 Register Map
ADDRESS TYPE RESET REGISTER NAME REGISTER DESCRIPTION SECTION
00h R 51h MR0 Device Type; Most Significant Byte Go
01h R 10h MR1 Device Type: Least Significant Byte Go
02h R 06h MR2 Device Revision Go
03h R 80h MR3 Vendor ID Byte 0 Go
04h R 97h MR4 Vendor ID Byte 1 Go
07h RW 0Eh MR7 Device Configuration - HID Go
12h RW 00h MR18 Device Configuration Go
13h W1C 00h MR19 Clear Register MR51 Temperature Status Command Go
14h W1C 00h MR20 Clear Register MR52 Error Status Command Go
1Ah RW 00h MR26 TS Configuration Go
1Bh RW 00h MR27 Interrupt Configurations Go
1Ch RW 70h MR28 TS Temp High Limit Configuration - Low Byte Go
1Dh RW 03h MR29 TS Temp High Limit Configuration - High Byte Go
1Eh RW 00h MR30 TS Temp Low Limit Configuration - Low Byte Go
1Fh RW 00h MR31 TS Temp Low Limit Configuration - High Byte Go
20h RW 50h MR32 TS Critical Temp High Limit Configuration - Low Byte Go
21h RW 05h MR33 TS Critical Temp High Limit Configuration - High Byte Go
22h RW 00h MR34 TS Critical Temp Low Limit Configuration - Low Byte Go
23h RW 00h MR35 TS Critical Temp Low Limit Configuration - High Byte Go
30h R 00h MR48 Device Status Go
31h R 00h MR49 TS Current Sensed Temperature - Low Byte Go
32h R 00h MR50 TS Current Sensed Temperature - High Byte Go
33h R 00h MR51 TS Temperature Status Go
34h R 00h MR52 Miscellaneous Error Status Go
Table 7-12 Register Section Access Type Codes
Access Type Code Description
Read Type
R R Read
RC R
C		 Read
to Clear
RV RV Reserved for future expansion
Write Type
W W Write
W1C W
1C		 W
1 to clear
Reset or Default Value
-n Value after reset or the default value

7.6.1 MR0: Device Type, Most Significant Byte (address = 00h) [reset = 51h]

Return to Register Map.

Figure 7-47 MR0: Device Type Register
7 6 5 4 3 2 1 0
MSB_DEV_TYPE[7:0]
R-51h
Table 7-13 MR0: Device Type Field Descriptions
Bit Field Type Reset Description
7:0 MSB_DEV_TYPE[7:0] R 51h Device type most significant byte. Used in conjunction with MR1 register.

7.6.2 MR1: Device Type, Least Significant Byte (address = 01h) [reset = 10h]

Return to Register Map.

Figure 7-48 MR1: Device Type Register
7 6 5 4 3 2 1 0
LSB_DEV_TYPE[7:0]
R-10h
Table 7-14 MR1: Device Type Field Descriptions
Bit Field Type Reset Description
7:0 LSB_DEV_TYPE[7:0] R 10h Device type least significant byte. Used in conjunction with MR0 register.
Indicates a Grade-B temperature sensor

7.6.3 MR2: Device Revision (address = 02h) [reset = 06h]

Return to Register Map.

Figure 7-49 MR2: Device Revision Register
7 6 5 4 3 2 1 0
Reserved DEV_REV_MAJOR[1:0] DEV_REV_MINOR[2:0] Reserved
R-00 R-00 R-011 R-0
Table 7-15 MR2: Device Revision Field Descriptions
Bit Field Type Reset Description
7:6 Reserved R 00 Reserved
5:4 DEV_REV_MAJOR[1:0] R 00 Indicates the major revision number
3:1 DEV_REV_MINOR[2:0] R 011 Indicates the minor revision number
0 Reserved R 0 Reserved

7.6.4 MR3: Vendor ID Byte 0 (address = 03h) [reset = 80h]

Return to Register Map.

Figure 7-50 MR3: Vendor ID Byte 0 Register
7 6 5 4 3 2 1 0
VENDOR_ID_BYTE0[7:0]
R-80h
Table 7-16 MR3: Vendor ID Byte 0 Field Descriptions
Bit Field Type Reset Description
7:6 VENDOR_ID_BYTE0[7:0] R 80h Indicates the lower byte of the Vendor ID.

7.6.5 MR4: Vendor ID Byte 1 (address = 04h) [reset = 97h]

Return to Register Map.

Figure 7-51 MR4: Vendor ID Byte 1 Register
7 6 5 4 3 2 1 0
VENDOR_ID_BYTE1[7:0]
R-97h
Table 7-17 MR4: Vendor ID Byte 1 Field Descriptions
Bit Field Type Reset Description
7:6 VENDOR_ID_BYTE1[7:0] R 97h Indicates the upper byte of the Vendor ID.

7.6.6 MR7: Device Configuration - HID (address = 07h) [reset = 0Eh]

The MR7 register reads the HID configured by the host controller. This register can only be updated by the SETHID CCC when device is in I2C, by the RSTDAA when the device is in I3C mode, or by a bus reset.

Return to Register Map.

Figure 7-52 MR7: Device Configuration - HID Register
7 6 5 4 3 2 1 0
Reserved DEV_HID_CODE[2:0] Reserved
R-0h RW-111 R-0
Table 7-18 MR7: Device Configuration - HID Field Descriptions
Bit Field Type Reset Description
7:4 Reserved R 0h Reserved
3:1 DEV_HID_CODE[2:0] RW 111 Device HID Code. The TMP139 device responds to unique 7-bit address as formed by a 4-bit LID code as Table 7-4 and 3-bit HID code as configured in this register.1
0 Reserved R 0 Reserved
  1. This register is updated only when SETHID CCC is sent to the TMP139 or when the device goes through a bus reset sequence.
Note:

Any host transaction which results in write or update to MR7 register must be immediately followed by a Stop condition. A Repeated Start may result in unpredictable behavior.

7.6.7 MR18: Device Configuration (address = 12h) [reset = 00h]

The MR18 register is used to configure the device features. In I3C mode, it allows the PEC to be enabled and Parity (T-bit) to be disabled. It also controls the default read address mode for both I2C and I3C bus operations. The burst length for the PEC byte is allowed only in I3C mode and the host controller must not update the bit in the I2C mode of operation.

Return to Register Map.

Figure 7-53 MR18: Device Configuration Register
7 6 5 4 3 2 1 0
PEC_EN PAR_DIS INF_SEL DEF_RD_ADDR_POINT_EN DEF_RD_ADDR_POINT_Start[1:0] DEF_RD_ADDR_POINT_BL Reserved
RW-0 RW-0 R-0 RW-0 RW-0 RW-0 R-0
Table 7-19 MR18: Device Configuration Field Descriptions
Bit Field Type Reset Description
7 PEC_EN RW 0 PEC enable1
0 = PEC is disabled
1 = PEC is enabled
6 PAR_DIS RW 0 Parity (T-bit) disable1
0 = Parity or T-bit is enabled
1 = Parity or T-bit is disabled
5 INF_SEL R 0 Interface selection
0 = I2C protocol (maximum speed of 1 MHz)
1 = I3C basic protocol
4 DEF_RD_ADDR_POINT_EN RW 0 Default read address pointer enable
0 = Disable default read address pointer (address pointer is set by host)
1 = Enable default read address pointer (address selected by MR18 register, DEF_RD_ADDR_POINT_Start[1:0] bits
3:2 DEF_RD_ADDR_POINT_Start[1:0] RW 00 Default read address pointer starting address2
00 = MR49 register
01 = Reserved
10 = Reserved
11 = Reserved
1 DEF_RD_ADDR_POINT_BL RW 0 Burst length for read pointer address for PEC calculation
0 = 2 bytes
1 = 4 bytes
0 Reserved R 0 Reserved
  1. PEC enable and parity disable are automatically updated when RSTDAA CCC is issued on the bus or a bus reset sequence is applied.
  2. Setting any of the reserved values shall result in unpredictable behavior from TMP139.
Note:

Any host transaction which results in write or update to MR18 register must be immediately followed by a Stop condition. A Repeated Start may result in unpredictable behavior.

7.6.8 MR19: Clear MR51 Temperature Status Command (address = 13h) [reset = 00h]

The MR19 register is written by the host to clear status for the temperature comparison after the most recent conversion.

Return to Register Map.

Figure 7-54 MR19: Clear MR51 Temperature Status Command Register
7 6 5 4 3 2 1 0
Reserved CLR_TS_CRIT_LOW CLR_TS_CRIT_HIGH CLR_TS_LOW CLR_TS_HIGH
R-0h R0-W1C R0-W1C R0-W1C R0-W1C
Table 7-20 MR19: Clear MR51 Temperature Status Command Field Descriptions
Bit Field Type Reset Description
7:4 Reserved R 0h Reserved
3 CLR_TS_CRIT_LOW R0-W1C 0 Clear temperature sensor critical low status
1 = Write '1' to clear MR51 TS_CRIT_LOW_STATUS bit
Writing a '0' has no effect on MR51 TS_CRIT_LOW_STATUS bit
2 CLR_TS_CRIT_HIGH R0-W1C 0 Clear temperature sensor critical high status
1 = Write '1' to clear MR51 TS_CRIT_HIGH_STATUS bit
Writing a '0' has no effect on MR51 TS_CRIT_HIGH_STATUS bit
1 CLR_TS_LOW R0-W1C 0 Clear temperature sensor low status
1 = Write '1' to clear MR51 TS_LOW_STATUS bit
Writing a '0' has no effect on MR51 TS_LOW_STATUS bit
0 CLR_TS_HIGH R0-W1C 0 Clear temperature sensor high status
1 = Write '1' to clear MR51 TS_HIGH_STATUS bit
Writing a '0' has no effect on MR51 TS_HIGH_STATUS bit

7.6.9 MR20: Clear MR52 Error Status Command (address = 14h) [reset = 00h]

The MR20 register is written by the host to clear error condition when the PEC checksum is incorrect or when the last write from the host results in a parity error in the T-bit. This register is valid in I3C mode only.

Return to Register Map.

Figure 7-55 MR20: Clear MR52 Error Status Command Register
7 6 5 4 3 2 1 0
Reserved CLR_PEC_ERROR CLR_PAR_ERROR
R-00h W1C W1C
Table 7-21 MR20: Clear MR52 Error Status Command Field Descriptions
Bit Field Type Reset Description
7:2 Reserved R 00h Reserved
1 CLR_PEC_ERROR R0-W1C 0 Clear packet error status
1 = Write '1' to clear MR52 PEC_ERROR_STATUS bit
Writing a '0' has no effect on MR52 PEC_ERROR_STATUS bit
0 CLR_PAR_ERROR R0-W1C 0 Clear parity error status
1 = Write '1' to clear MR52 PEC_ERROR_STATUS bit
Writing a '0' has no effect on MR52 PAR_ERROR_STATUS bit

7.6.10 MR26: TS Configuration (address = 1Ah) [reset = 00h]

The MR26 register may be used by the host to disable the temperature sensor. The device will stop temperature conversion or, if there is an ongoing conversion when the bit is set, then it shall complete the current conversion and then disable the temperature sensor.

Return to Register Map.

Figure 7-56 MR26: Temperature Sensor Configuration Register
7 6 5 4 3 2 1 0
Reserved DIS_TS
R-00h RW-0
Table 7-22 MR26: Temperature Sensor Configuration Field Descriptions
Bit Field Type Reset Description
7:1 Reserved R 00h Reserved
0 DIS_TS RW 0 Disable temperature sensor
0 = Enable temperature sensor.
1 = Disable temperature sensor.

7.6.11 MR27: Interrupt Configuration (address = 1Bh) [reset = 00h]

Return to Register Map.

Figure 7-57 MR27: Interrupt Configuration Register
7 6 5 4 3 2 1 0
CLR_GLOBAL Reserved IBI_ERROR_EN IBI_TS_CRIT_LOW_EN IBI_TS_CRIT_HIGH_EN IBI_TS_LOW_EN IBI_TS_HIGH_EN
W1C R-00 R-0 RW-0 RW-0 RW-0 RW-0
Table 7-23 MR27: Interrupt Configuration Field Descriptions
Bit Field Type Reset Description
7 CLR_GLOBAL R0-W1C 0 Global clear event status and In Band Interrupt (IBI) status
1 = Write '1' to clear the registers MR48, MR51 and MR52.
Writing a '0' has no effect on registers MR48, MR51 and MR52.
6:5 Reserved R 00 Reserved
4 IBI_ERROR_EN R 0 In band interrupt (IBI) enable for MR52 error log.1
0 = Disable. Errors logged in MR52 register bits do not generate an IBI to host.
1 = Enable. Errors logged in MR52 register bits generate an IBI to host.
3 IBI_TS_CRIT_LOW_EN RW 0 In band interrupt (IBI) enable for temperature sensor critical low.
0 = Disable. MR51 register TS_CRIT_LOW_STATUS bit does not generate an IBI to host.
1 = Enable. MR51 register TS_CRIT_LOW_STATUS bit generates an IBI to host.
2 IBI_TS_CRIT_HIGH_EN RW 0 In band interrupt (IBI) enable for temperature sensor critical high.
0 = Disable. MR51 register TS_CRIT_HIGH_STATUS bit does not generate an IBI to host.
1 = Enable. MR51 register TS_CRIT_HIGH_STATUS bit generates an IBI to host.
1 IBI_TS_LOW_EN RW 0 In band interrupt (IBI) enable for temperature sensor low.
0 = Disable. MR51 register TS_LOW_STATUS bit does not generate an IBI to host.
1 = Enable. MR51 register TS_LOW_STATUS bit generates an IBI to host.
0 IBI_TS_HIGH_EN RW 0 In band interrupt (IBI) enable for temperature sensor high.
0 = Disable. MR51 register TS_HIGH_STATUS bit does not generate an IBI to host.
1 = Enable. MR51 register TS_HIGH_STATUS bit generates an IBI to host.
  1. IBI_ERROR_EN can only be updated by ENEC CCC, DISEC CCC, RSTDAA CCC or bus reset sequence. A direct write to the register or through DEVCTRL CCC shall not update the bit and may lead to unpredictable behavior.

7.6.12 MR28: Temperature Sensor High Limit-Low Byte Configuration (address = 1Ch) [reset = 70h]

The status flag for temperature high limit is set when the result of the temperature conversion is greater than the programmed value in the MR29 and MR28 registers. The application must ensure that the critical temperature high limit registers must have a value greater than the temperature high limit registers.

Return to Register Map.

Figure 7-58 MR28: Temperature Sensor High Limit-Low Byte Configuration Register
7 6 5 4 3 2 1 0
TS_HIGH_LIMIT_LOW[7:0]
RW-70h R-0 R-0
Table 7-24 MR28: Temperature Sensor High Limit-Low Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_HIGH_LIMIT_LOW[7:0] RW 70h Low byte of the high limit temperature for the thermal sensor.1
MR29 and MR28 together define the high limit for the thermal sensor.
  1. The bits marked as R-0, shall not be updated when host writes 1 and shall read as 0.

7.6.13 MR29: Temperature Sensor High Limit-High Byte Configuration (address = 1Dh) [reset = 03h]

The status flag for temperature high limit is set when the result of the temperature conversion is greater than the programmed value in the MR29 and MR28 registers. The application must ensure that the critical temperature high limit registers must have a value greater than the temperature high limit registers.

Return to Register Map.

Figure 7-59 MR29: Temperature Sensor High Limit-High Byte Configuration Register
7 6 5 4 3 2 1 0
TS_HIGH_LIMIT_HIGH[7:0]
R-0 R-0 R-0 RW-03h
Table 7-25 MR29: Temperature Sensor High Limit-High Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_HIGH_LIMIT_HIGH[7:0] RW 03h High byte of the high limit temperature for the thermal sensor.1
MR29 and MR28 together define the high limit for the thermal sensor.
  1. The bits marked as R-0, shall not be updated when host writes 1 and shall read as 0.

7.6.14 MR30: Temperature Sensor Low Limit-Low Byte Configuration (address = 1Eh) [reset = 00h]

The status flag for critical low limit is set when the result of the temperature conversion is less than the programmed value in the MR31 and MR30 registers. The application must ensure that the critical temperature low limit registers must have a value lower than the temperature low limit registers.

Return to Register Map.

Figure 7-60 MR30: Temperature Sensor Low Limit-Low Byte Configuration Register
7 6 5 4 3 2 1 0
TS_LOW_LIMIT_LOW[7:0]
RW-00h R-0 R-0
Table 7-26 MR30: Temperature Sensor Low Limit-Low Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_LOW_LIMIT_LOW[7:0] RW 00h Low byte of the low limit temperature for the thermal sensor.1
MR31 and MR30 together define the low limit for the thermal sensor.
  1. The bits marked as R-0, shall not be updated when host writes 1 and shall read as 0.

7.6.15 MR31: Temperature Sensor Low Limit-High Byte Configuration (address = 1Fh) [reset = 00h]

The status flag for critical low limit is set when the result of the temperature conversion is less than the programmed value in the MR31 and MR30 registers. The application must ensure that the critical temperature low limit registers must have a value lower than the temperature low limit registers.

Return to Register Map.

Figure 7-61 MR31: Temperature Sensor Low Limit-High Byte Configuration Register
7 6 5 4 3 2 1 0
TS_LOW_LIMIT_HIGH[7:0]
R-0 R-0 R-0 RW-00h
Table 7-27 MR31: Temperature Sensor Low Limit-High Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_LOW_LIMIT_HIGH[7:0] RW 00h High byte of the low limit temperature for the thermal sensor.1
MR31 and MR30 together define the low limit for the thermal sensor.
  1. The bits marked as R-0, shall not be updated when host writes 1 and shall read as 0.

7.6.16 MR32: Temperature Sensor Critical High Temperature Limit-Low Byte Configuration (address = 20h) [reset = 50h]

The status flag for critical temperature high limit is set when the result of the temperature conversion is greater than the programmed value in the MR33 and MR32 registers. The application must ensure that the critical temperature high limit registers must have a value greater than the temperature high limit registers.

Return to Register Map.

Figure 7-62 MR32: Temperature Sensor Critical Temperature High Limit-Low Byte Configuration Register
7 6 5 4 3 2 1 0
TS_CRIT_HIGH_LIMIT_LOW[7:0]
RW-50h R-0 R-0
Table 7-28 MR32: Temperature Sensor Critical Temperature High Limit-Low Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_CRIT_HIGH_LIMIT_LOW[7:0] RW 50h Low byte of the critical high limit temperature for the thermal sensor.1
MR33 and MR32 together define the critical high limit temperature for the thermal sensor.
  1. The bits marked as R-0, shall not be updated when host writes 1 and shall read as 0.

7.6.17 MR33: Temperature Sensor Critical Temperature High Limit-High Byte Configuration (address = 21h) [reset = 05h]

The status flag for critical temperature high limit is set when the result of the temperature conversion is greater than the programmed value in the MR33 and MR32 registers. The application must ensure that the critical temperature high limit registers must have a value greater than the temperature high limit registers.

Return to Register Map.

Figure 7-63 MR33: Temperature Sensor Critical Temperature High Limit-High Byte Configuration Register
7 6 5 4 3 2 1 0
TS_CRIT_HIGH_LIMIT_HIGH[7:0]
R-0 R-0 R-0 RW-05h
Table 7-29 MR33: Temperature Sensor Critical Temperature High Limit-High Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_CRIT_HIGH_LIMIT_HIGH[7:0] RW 05h High byte of the critical high limit temperature for the thermal sensor.1
MR33 and MR32 together define the critical high limit temperature for the thermal sensor.
  1. The bits marked as R-0, shall not be updated when host writes 1 and shall read as 0.

7.6.18 MR34: Temperature Sensor Critical Temperature Low Limit-Low Byte Configuration (address = 22h) [reset = 00h]

The status flag for critical temperature low limit is set when the result of the temperature conversion is less than the programmed value in the MR35 and MR34 registers. The application must ensure that the critical temperature low limit registers must have a value lesser than the temperature low limit registers.

Return to Register Map.

Figure 7-64 MR34: Temperature Sensor Critical Temperature Low Limit-Low Byte Configuration Register
7 6 5 4 3 2 1 0
TS_CRIT_LOW_LIMIT_LOW[7:0]
RW-00h R-0 R-0
Table 7-30 MR34: Temperature Sensor Critical Temperature Low Limit-Low Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_CRIT_LOW_LIMIT_LOW[7:0] RW 00h Low byte of the critical low limit temperature for the thermal sensor.1
MR35 and MR34 together define the critical low limit temperature for the thermal sensor.
  1. The bits marked as R-0, shall not be updated when host writes 1 and shall read as 0.

7.6.19 MR35: Temperature Sensor Critical Temperature Low Limit-High Byte Configuration (address = 23h) [reset = 00h]

The status flag for critical temperature low limit is set when the result of the temperature conversion is less than the programmed value in the MR35 and MR34 registers. The application must ensure that the critical temperature low limit registers must have a value lesser than the temperature low limit registers.

Return to Register Map.

Figure 7-65 MR35: Temperature Sensor Critical Temperature Low Limit-High Byte Configuration Register
7 6 5 4 3 2 1 0
TS_CRIT_LOW_LIMIT_HIGH[7:0]
R-0 R-0 R-0 RW-00h
Table 7-31 MR35: Temperature Sensor Critical Temperature Low Limit-High Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_CRIT_LOW_LIMIT_HIGH[7:0] RW 00h High byte of the critical low limit temperature for the thermal sensor.1
MR35 and MR34 together define the critical low limit temperature for the thermal sensor.
  1. The bits marked as R-0, shall not be updated when host writes 1 and shall read as 0.

7.6.20 MR48: Device Status (address = 30h) [reset = 00h]

The MR48 register provides the status of the IBI when the TMP139 is in I3C mode.

Return to Register Map.

Figure 7-66 MR48: Device Status Register
7 6 5 4 3 2 1 0
IBI_STATUS Reserved
R-0 R-00h
Table 7-32 MR48: Device Status Field Descriptions
Bit Field Type Reset Description
7 IBI_STATUS R 0 Device event In Band Interrupt (IBI) status.
0 = No pending IBI.
1 = Pending IBI.
6:0 Reserved R 00h Reserved

7.6.21 MR49: Current Sensed Temperature Low Byte (address = 31h) [reset = 00h]

The MR49 register, stores the lower 8-bits of the temperature output from the most recent conversion.

Return to Register Map.

Figure 7-67 MR49: Current Sensed Temperature Low Byte Register
7 6 5 4 3 2 1 0
TS_SENSE_LOW[7:0]
R-00h
Table 7-33 MR49: Current Sensed Temperature Low Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_SENSE_LOW[7:0] R 00h Low byte of the of the current temperature returned after most recent conversion by the thermal sensor.
MR50 and MR49 together provide the temperature returned after the most recent conversion.

7.6.22 MR50: Current Sensed Temperature High Byte (address = 32h) [reset = 00h]

The MR50 register, stores the upper 8-bits of the temperature output from the most recent conversion..

Return to Register Map.

Figure 7-68 MR50: Current Sensed Temperature High Byte Configuration Register
7 6 5 4 3 2 1 0
TS_SENSE_HIGH[7:0]
R-00h
Table 7-34 MR50: Current Sensed Temperature High Byte Field Descriptions
Bit Field Type Reset Description
7:0 TS_SENSE_HIGH[7:0] R 00h High byte of the of the current temperature returned after most recent conversion by the thermal sensor.
MR49 and MR50 together provide the temperature returned after the most recent conversion.

7.6.23 MR51: Temperature Status (address = 33h) [reset = 00h]

The MR51 registers stores the status from comparison of the most recent conversion temperature output to each of the four threshold levels defined in MR28 to MR35.

Return to Register Map.

Figure 7-69 MR51: Temperature Status Register
7 6 5 4 3 2 1 0
Reserved TS_CRIT_LOW_STATUS TS_CRIT_HIGH_STATUS TS_LOW_STATUS TS_HIGH_STATUS
R-0h R-0 R-0 R-0 R-0
Table 7-35 MR51: Temperature Status Field Descriptions
Bit Field Type Reset Description
6:5 Reserved R 00 Reserved
3 TS_CRIT_LOW_STATUS R 0 Temperature sensor critical low status.
0 = Temperature is above the limit set in registers MR35 and MR34.
1 = Temperature is below the limit set in registers MR35 and MR34.
2 TS_CRIT_HIGH_STATUS R 0 Temperature sensor critical high status.
0 = Temperature is below the limit set in registers MR33 and MR32.
1 = Temperature is above the limit set in registers MR33 and MR32.
1 TS_LOW_STATUS R 0 Temperature sensor low status.
0 = Temperature is above the limit set in registers MR31 and MR30.
1 = Temperature is below the limit set in registers MR31 and MR30.
0 TS_HIGH_STATUS R 0 Temperature sensor high status
0 = Temperature is below the limit set in registers MR29 and MR28.
1 = Temperature is above the limit set in registers MR29 and MR28.

7.6.24 MR52: Miscellaneous Error Status (address = 34h) [reset = 00h]

The MR52 register stores the status for PEC checksum failure when PEC mode is enabled and parity error on the T-bit when the host writes to the device in I3C mode.

Return to Register Map.

Figure 7-70 MR52: Miscellaneous Error Status Register
7 6 5 4 3 2 1 0
Reserved PEC_ERROR_STATUS PAR_ERROR_STATUS
R-00h R-0 R-0
Table 7-36 MR52: Miscellaneous Error Status Field Descriptions
Bit Field Type Reset Description
7:2 Reserved R 00 Reserved
1 PEC_ERROR_STATUS R 0 Packet error status.
0 = No PEC error.
1 = PEC error in one or more packets.
0 PAR_ERROR_STATUS R 0 Parity check error status
0 = No parity error.
1 = Parity error in one or more bytes.