SNIS217C december   2020  – may 2023 TMP139

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down and Device Reset
      3. 7.3.3 Temperature Result and Limits
      4. 7.3.4 Bus Reset
      5. 7.3.5 Interrupt Generation
      6. 7.3.6 Parity Error Check
      7. 7.3.7 Packet Error Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Mode
      2. 7.4.2 Serial Address
      3. 7.4.3 I2C Mode Operation
        1. 7.4.3.1 Host I2C Write Operation
        2. 7.4.3.2 Host I2C Read Operation
        3. 7.4.3.3 Host I2C Read Operation in Default Read Address Pointer Mode
        4. 7.4.3.4 Switching from I2C Mode to I3C Basic Mode
      4. 7.4.4 I3C Basic Mode Operation
        1. 7.4.4.1 Host I3C Write Operation without PEC
        2. 7.4.4.2 Host I3C Write Operation with PEC
        3. 7.4.4.3 Host I3C Read Operation without PEC
        4. 7.4.4.4 Host I3C Read Operation with PEC
        5. 7.4.4.5 Host I3C Read Operation in Default Read Address Pointer Mode
      5. 7.4.5 In Band Interrupt
        1. 7.4.5.1 In Band Interrupt Arbitration Rules
        2. 7.4.5.2 In Band Interrupt Bus Transaction
      6. 7.4.6 Common Command Codes Support
        1. 7.4.6.1 ENEC CCC
        2. 7.4.6.2 DISEC CCC
        3. 7.4.6.3 RSTDAA CCC
        4. 7.4.6.4 SETAASA CCC
        5. 7.4.6.5 GETSTATUS CCC
        6. 7.4.6.6 DEVCAP CCC
        7. 7.4.6.7 SETHID CCC
        8. 7.4.6.8 DEVCTRL CCC
      7. 7.4.7 I/O Operation
      8. 7.4.8 Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1 Enabling Interrupt Mechanism
      2. 7.5.2 Clearing Interrupt
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.6.8 DEVCTRL CCC

The DEVCTRL CCC is issued by the host controller for enable or disable operations that are common to devices on the bus and TMP139 shall recognize the DEVCTRL CCC.

The command is generally issued in broadcast mode, but may be issued as unicast or multicast mode as well. The host may issue the DEVCTRL CCC as a generic access with RegMod field set as 0 or for a specific register access with RegMod set as 1. When RegMod field is set to 0, Figure 7-41 shows the DEVCTRL CCC packet structure when PEC is disabled. Figure 7-42 shows the structure of the DEVCTRL CCC when RegMod field is set to 0 and PEC is enabled. In the latter case the host controller shall append the PEC byte calculated on all bytes except the byte with 7'h7E and R/W=0 after the Start or Repeated Start.

GUID-F9D5A4C8-32E7-44BD-BEB3-A2534CD032A7-low.gifFigure 7-41 DEVCTRL CCC With REGMOD = 0 and PEC Disabled
GUID-1C89C26D-687E-4D0A-A215-A9F91243839B-low.gifFigure 7-42 DEVCTRL CCC With REGMOD = 0 and PEC Enabled

When RegMod field is set to 1, Figure 7-43 shows the DEVCTRL CCC packet structure when PEC is disabled. Figure 7-44 shows the structure of the DEVCTRL CCC when RegMod field is set to 1 and PEC is enabled. In the latter case the host controller shall append the PEC byte calculated on all bytes except the byte with 7'h7E and R/W = 0 after the Start or Repeated Start. If the CMD field indicates that there is only one byte to write, then the optional register data must not be sent by the host.

GUID-20200624-SS0I-693Z-FB3N-K2PCCVMC8M4V-low.gif Figure 7-43 DEVCTRL CCC With REGMOD = 1 and PEC Disabled.
GUID-30C48CE4-DB0F-48AC-A16D-71ABC531BE4B-low.gifFigure 7-44 DEVCTRL CCC With REGMOD = 1 and PEC Enabled

Note:

TMP139 NACKs the DEVCTRL CCC if the previous transaction has a parity or PEC error and the host starts the transaction with a Repeated Start.

The Table 7-8 describes the definition of the command fields.

Table 7-8 DEVCTRL CCC Command Definitions
FieldDescriptionValuesAction
ADDRMASK[2:0]Broadcast, multicast or unicast selection000 = Unicast commandTMP139 matches the DEVADDR[6:0] field with its serial address .
011 = Multicast commandTMP139 matches the DEVADDR[6:3] field with its LID code in the serial address.
111 = Broadcast commandTMP139 ignores the DEVADDR[6:0] and performs the required action.
STOFFSET[1:0]Start offset byte00 = Byte 0TMP139 identifies which byte is the first byte out of DEVCTRL DATA 0, DEVCTRL DATA 1, DEVCTRL DATA 2 and DEVCTRL DATA 3 and updates its register accordingly.
This field is valid only when REGMOD = 0.
01 = Byte 1
10 = Byte 2
11 = Byte 3
PECBL[1:0]Identifies the burst length for PEC byte position00 = 1 ByteTMP139 identifies the position of the PEC byte after the DEVCTRL DATA bytes are sent.
This field is valid only when REGMOD = 0 and PEC is enabled.
01 = 2 Byte
10 = 3 Byte
11 = 4 Byte
REGMODIdentifies if it is a generic or specific register access0 = Generic AccessTMP139 understand the DEVCTRL DATA byte as generic data bytes described in Table 7-9
1 = Register AccessTMP139 understand the DEVCTRL DATA byte as specific register access bytes.
If PEC is disabled, the format used for specific register access is as per Figure 7-11.
If PEC is enabled, the format used for specific register access is as per Figure 7-13
Table 7-9 Generic Data Byte Format
DEVCTRL DATA BitFunctionValuesAction
DEVCTRL DATA 0 [7]PEC Enable0 = DisableMR18 register PEC_EN bit is updated
1 = Enable
DEVCTRL DATA 0 [6]Parity Disable0 = EnableMR18 register PAR_DIS bit is updated
1 = Disable
DEVCTRL DATA 0 [5:0]ReservedReserved
DEVCTRL DATA 1 [7:4]ReservedReserved
DEVCTRL DATA 1 [3]Global IBI Clear0 = No actionMR27 register CLR_GLOBAL bit is updated
1 = Clear all events and pending IBI
DEVCTRL DATA 1 [2:0]ReservedReserved
DEVCTRL DATA 2 [7:0]ReservedReserved
DEVCTRL DATA 3 [7:0]ReservedReserved
Note:

TMP139 NACKs the DEVCTRL CCC if the previous transaction has a parity or PEC error and the host starts the transaction with a Repeated Start.