SNIS217C december   2020  – may 2023 TMP139

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power-Up Sequence
      2. 7.3.2 Power-Down and Device Reset
      3. 7.3.3 Temperature Result and Limits
      4. 7.3.4 Bus Reset
      5. 7.3.5 Interrupt Generation
      6. 7.3.6 Parity Error Check
      7. 7.3.7 Packet Error Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 Conversion Mode
      2. 7.4.2 Serial Address
      3. 7.4.3 I2C Mode Operation
        1. 7.4.3.1 Host I2C Write Operation
        2. 7.4.3.2 Host I2C Read Operation
        3. 7.4.3.3 Host I2C Read Operation in Default Read Address Pointer Mode
        4. 7.4.3.4 Switching from I2C Mode to I3C Basic Mode
      4. 7.4.4 I3C Basic Mode Operation
        1. 7.4.4.1 Host I3C Write Operation without PEC
        2. 7.4.4.2 Host I3C Write Operation with PEC
        3. 7.4.4.3 Host I3C Read Operation without PEC
        4. 7.4.4.4 Host I3C Read Operation with PEC
        5. 7.4.4.5 Host I3C Read Operation in Default Read Address Pointer Mode
      5. 7.4.5 In Band Interrupt
        1. 7.4.5.1 In Band Interrupt Arbitration Rules
        2. 7.4.5.2 In Band Interrupt Bus Transaction
      6. 7.4.6 Common Command Codes Support
        1. 7.4.6.1 ENEC CCC
        2. 7.4.6.2 DISEC CCC
        3. 7.4.6.3 RSTDAA CCC
        4. 7.4.6.4 SETAASA CCC
        5. 7.4.6.5 GETSTATUS CCC
        6. 7.4.6.6 DEVCAP CCC
        7. 7.4.6.7 SETHID CCC
        8. 7.4.6.8 DEVCTRL CCC
      7. 7.4.7 I/O Operation
      8. 7.4.8 Timing Diagrams
    5. 7.5 Programming
      1. 7.5.1 Enabling Interrupt Mechanism
      2. 7.5.2 Clearing Interrupt
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YAH|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.8 Timing Diagrams

The TMP139 is a I2C and I3C interface-compatible device. Figure 6-1 to Figure 6-3 describe the various bus conditions that are supported on the bus. The following lists the definitions for the bus conditions:

  1. Bus Idle: Both SDA and SCL lines remain high after a Stop condition.
  2. Start (S) condition: A change in the state of the SDA line from high to low, when the SCL is high defines a Start condition. The Start condition is preceded by a bus idle.
  3. Stop (P) condition: A change in the state of the SDA line from low to high, when the SCL is high defines a Stop condition.
  4. Repeated Start (SR) condition: A change in the state of the SDA line from high to low, when the SCL is high and is preceded by a data transfer defines a Repeated Start condition.
  5. Data Transfer: The number of data bytes transferred between a Start and Stop condition and determined by the host or device.
  6. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge (ACK) bit during device address and host to device write transfer. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. On a host receive, the termination of the data transfer can be signaled by the host generating a Not-Acknowledge (NAK) on the last byte that is transmitted by the target device. This behavior is as per I2C mode of operation.

    During I3C mode of operation. each receiving device shall only acknowledge its device address. Additionally, the host shall acknowledge the device address during a successful IBI address arbitration.

  7. T-Bit: The T-bit is only applicable in I3C mode of operation or when the host sends a common command code (CCC) during I2C mode of operation. The T-bit contains the parity information when the host writes to the targeted device(s). During a read, if the T-bit is sampled as 1 on the rising edge of the 9th clock, the bit indicates a continuation of a read by the device. If a host wants to terminate the read, then the host can activate the pullup while the device drives the line high as shown in Figure 6-2. When the device stops driving the line and tri-states its output, the pull up keeps the line high momentarily before the host claims control of the bus to generate a Repeated Start and Stop to end the read. If the host can accept more data from the device, the host must not drive the line. The device samples the SDA on the falling edge of the 9th clock, and if the T-bit is sampled as 1, the device resumes driving the SDA for the next byte. During a read, if the T-bit is sampled as 0 on the rising edge of the 9th clock, the bit is used to indicate a termination of the read by the device as shown in Figure 6-3. The host shall also drive the SDA low, such that when the device stops driving the line and tri-states its output, the host has control of the bus to generate a Stop to end the read.