SBOS939C April   2019  – November 2019 TMP235-Q1 , TMP236-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Functional Block Diagram
      2.      Output Voltage vs Ambient
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Connection to an ADC
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Design Requirements

See Figure 10 for suggested connections to an ADC input stage. Most CMOS-based ADCs have a sampled data comparator input structure. When the ADC charges the sampling capacitor (CSAMPLE), the capacitor requires instantaneous charge from the output of the analog source temperature sensor, such as the TMP235-Q1. Therefore, the output impedance of the temperature sensor can affect ADC performance. In most cases, adding an external capacitor (CFILTER) mitigates design challenges. The TMP235-Q1 is specified and characterized with a 1000-pF maximum capacitive load (CLOAD). Figure 10 shows CLOAD as the sum of CFILTER + CMUX + CSAMPLE. TI recommends maximizing the CFILTER value while allowing for the maximum specified ADC input capacitance (CMUX + CSAMPLE) to limit the total CLOAD at 1000 pF. In most cases, a 680-pF CFILTER provides a reasonable allowance for ADC input capacitance to minimize ADC sampling error and reduce noise coupling. An optional series resistor (RFILTER) and CFILTER provides additional low-pass filtering to reject system level noise. TI recommends placing RFILTER and CFILTER as close as possible to the ADC input for optimal performance.