SNIS218B September   2019  – June 2022 TMP390-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TMP390-Q1 Programming Tables
      2. 7.3.2 Trip Test
      3. 7.3.3 20°C Hysteresis
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Applications Information
    2. 8.2 Typical Applications
      1. 8.2.1 Simplified Application Schematic
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 8.2.2 TMP390-Q1 With 10°C Hysteresis
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      3. 8.2.3 One Channel Operation for Hot Trip Point up to 124°C
        1. Application Curve
      4. 8.2.4 One Channel Operation for Cold Trip Point
        1. Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Design Requirements

The TMP390-Q1 requires two resistors to set the high and low trip points and hysteresis, and two pullup resistors for the open-drain device. TI also highly recommends to place a 0.1-µF, power-supply bypassing capacitor close to the VDD supply pin. To minimize the internal power dissipation, use two pullup resistors greater than 1 kΩ from the OUTA and OUTB pins to the VDD pin. A separate supply, VDDIO, may be used for the pullup voltage to set the output voltage level to the level required by the MCU, as shown in Figure 8-1. The open-drain output gives flexibility of pulling up to any voltage independent of VDD (VDDIO must be less than or equal to VDD + 0.3 V). This allows for use of longer cables or different power supply options. If a separate voltage level is not required, TI recommends to tie the pullup to the TMP390-Q1 VDD.

If the SETA or SETB connected resistor value is outside the legal range, the associated output goes to permanent output zero stage and the channel cannot be used. The other channel still will be in operating condition, and device can be used in one channel mode. If the SETB input is grounded or left floating, the Channel B cannot be used and the hysteresis for Channel A will be 20°C. The SETA and SETB connected resistors are measured during POR. If two consecutive measurements are not matching each other, then the device sets the associated channel output to zero and repeats the resistor measurements until the measurements match. When the measurements match, the channel output is released. Note that it is possible to connect some device outputs together by shorting the OUTA or OUTB line.