SBOS527G December   2010  – September 2025 TMP411-Q1 , TMP411D-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (TMP411-Q1)
    6. 6.6  Electrical Characteristics (TMP411D-Q1)
    7. 6.7  Timing Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics (TMP411-Q1)
    10. 6.10 Typical Characteristics (TMP411D-Q1)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Series Resistance Cancellation
      2. 7.3.2 Differential Input Capacitance
      3. 7.3.3 Temperature Measurement Data
      4. 7.3.4 THERM (PIN 4) and ALERT/ THERM2 (PIN 6)
      5. 7.3.5 Sensor Fault
      6. 7.3.6 Undervoltage Lockout (TMP411-Q1 Only)
      7. 7.3.7 Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
      2. 7.4.2 One-Shot Conversion
    5. 7.5 Programming
      1. 7.5.1  Serial Interface
      2. 7.5.2  Bus Overview
      3. 7.5.3  Timing Diagrams
      4. 7.5.4  Serial Bus Address
      5. 7.5.5  Read/Write Operations
      6. 7.5.6  Time-Out Function
      7. 7.5.7  High-Speed Mode
      8. 7.5.8  General-Call Reset
      9. 7.5.9  Software Reset
      10. 7.5.10 SMBUS Alert Function
  9. 8 Register Map
    1. 8.1  Register Information
    2. 8.2  Pointer Register
    3. 8.3  Temperature Registers
    4. 8.4  Limit Registers
    5. 8.5  Status Register
    6. 8.6  Configuration Register
    7. 8.7  Resolution Register
    8. 8.8  Conversion Rate Register
    9. 8.9  N-factor Correction Register
    10. 8.10 Minimum and Maximum Registers
    11. 8.11 Consecutive Alert Register
    12. 8.12 THERM Hysteresis Register
    13. 8.13 Identification Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TMP411-Q1 and TMP411D-Q1 devices are dual-channel digital temperature sensors that combine a local die-temperature measurement channel and a remote junction-temperature measurement channel in a single VSSOP-8 or SOT23-8 package. The TMP411-Q1 and TMP411D-Q1 devices are two-wire-compatible and SMBus interface-compatible and are specified over an ambient temperature range of –40°C to 125°C. The TMP411-Q1 and TMP411D-Q1 devices contain multiple registers for holding configuration information, temperature measurement results, temperature comparator maximum/minimum limits, and status information.

User-programmed high- and low-temperature limits stored in the TMP411-Q1 and TMP411D-Q1 devices can be used to trigger an overtemperature alarm (ALERT) on local and remote temperatures. Additional thermal limits can be programmed into the TMP411-Q1 and TMP411D-Q1 devices and used to trigger another flag (THERM) that initiates a system response to rising temperatures.

The TMP411-Q1 and TMP411D-Q1 devices require only a transistor connected between D+ and D− for proper remote temperature sensing operation. The SCL and SDA interface pins require pullup resistors as part of the communication bus, whereas ALERT and THERM pins are open-drain outputs that also need pullup resistors. ALERT and THERM pins can be shared with other devices if desired for a wired-OR implementation. A 0.1μF power-supply bypass capacitor is recommended for good local bypassing. Figure 7-1 shows a typical configuration for the TMP411-Q1 and TMP411D-Q1 devices.

TMP411-Q1 TMP411D-Q1 Basic Connections
A. A diode-connected configuration provides better settling time. The transistor-connected configuration provides better series resistance cancellation. NPN transistors must be diode-connected. PNP transistors can either be transistor-connected or diode-connected. TI recommends this layout for the MMBT3906LP and MMBT3904LP devices.
B. RS (optional) must be < 1.5kΩ in most applications. Selection of RS depends on the specific application; see Filtering.
C. CDIFF (optional) must be < 1000pF in most applications. Selection of CDIFF depends on the specific application; see Filtering, Figure 6-12 (Figure 6-13 for the new chip), and Figure 6-28.
Figure 7-1 Basic Connections