SBOS527G December   2010  – September 2025 TMP411-Q1 , TMP411D-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (TMP411-Q1)
    6. 6.6  Electrical Characteristics (TMP411D-Q1)
    7. 6.7  Timing Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics (TMP411-Q1)
    10. 6.10 Typical Characteristics (TMP411D-Q1)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Series Resistance Cancellation
      2. 7.3.2 Differential Input Capacitance
      3. 7.3.3 Temperature Measurement Data
      4. 7.3.4 THERM (PIN 4) and ALERT/ THERM2 (PIN 6)
      5. 7.3.5 Sensor Fault
      6. 7.3.6 Undervoltage Lockout (TMP411-Q1 Only)
      7. 7.3.7 Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
      2. 7.4.2 One-Shot Conversion
    5. 7.5 Programming
      1. 7.5.1  Serial Interface
      2. 7.5.2  Bus Overview
      3. 7.5.3  Timing Diagrams
      4. 7.5.4  Serial Bus Address
      5. 7.5.5  Read/Write Operations
      6. 7.5.6  Time-Out Function
      7. 7.5.7  High-Speed Mode
      8. 7.5.8  General-Call Reset
      9. 7.5.9  Software Reset
      10. 7.5.10 SMBUS Alert Function
  9. 8 Register Map
    1. 8.1  Register Information
    2. 8.2  Pointer Register
    3. 8.3  Temperature Registers
    4. 8.4  Limit Registers
    5. 8.5  Status Register
    6. 8.6  Configuration Register
    7. 8.7  Resolution Register
    8. 8.8  Conversion Rate Register
    9. 8.9  N-factor Correction Register
    10. 8.10 Minimum and Maximum Registers
    11. 8.11 Consecutive Alert Register
    12. 8.12 THERM Hysteresis Register
    13. 8.13 Identification Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.3 Timing Diagrams

The TMP411-Q and TMP411D-Q1 devices are two-wire and SMBus-compatible. Figure 7-5 to Figure 7-8 describe the various operations on the TMP411-Q1 and TMP411D-Q1. Bus definitions are given as follows:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low (while the SCL line is high), defines a START condition. A START condition initiates each data transfer.

Stop Data Transfer: A change in the state of the SDA line from low to high (while the SCL line is high) defines a STOP condition. A STOP or repeated START condition terminates each data transfer.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the controller device. The receiver acknowledges the data transfer.

Acknowledge: Each receiving device (when addressed) is required to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a controller receive, the controller signals data transfer termination by generating a not-acknowledge bit transmitted by the controller.

TMP411-Q1 TMP411D-Q1 Two-Wire Timing Diagram for Write Word Format
A. Target address 1001 100 (TMP411A-Q1/TMP411DA-Q1 and TMP411D-Q1/TMP411DD-Q1) shown. Target address changes for TMP411B-Q1/TMP411DB-Q1 and TMP411C-Q1/TMP411DC-Q1. See the Ordering Information table for more details.
Figure 7-5 Two-Wire Timing Diagram for Write Word Format
TMP411-Q1 TMP411D-Q1 Two-Wire Timing Diagram for Single-Byte Read Format
A. Target address 1001 100 (TMP411A-Q1/TMP411DA-Q1 and TMP411D-Q1/TMP411DD-Q1) shown. Target address changes for TMP411B-Q1/TMP411DB-Q1 and TMP411C-Q1/TMP411DC-Q1. See the Ordering Information table for more details.
B. The host must leave SDA high to terminate a single-byte read operation.
Figure 7-6 Two-Wire Timing Diagram for Single-Byte Read Format
TMP411-Q1 TMP411D-Q1 Two-Wire Timing Diagram for Two-Byte Read Format
A. Target address 1001 100 (TMP411A-Q1/TMP411DA-Q1 and TMP411D-Q1/TMP411DD-Q1) shown. Target address changes for TMP411B-Q1/TMP411DB-Q1 and TMP411C-Q1/TMP411DC-Q1. See the Ordering Information table for more details.
B. The host must leave SDA high to terminate a two−byte read operation.
Figure 7-7 Two-Wire Timing Diagram for Two-Byte Read Format
TMP411-Q1 TMP411D-Q1 Timing Diagram for SMBus ALERT
A. Target address 1001 100 (TMP411A-Q1/TMP411DA-Q1 and TMP411D-Q1/TMP411DD-Q1) shown. Target address changes for TMP411B-Q1/TMP411DB-Q1 and TMP411C-Q1/TMP411DC-Q1. See the Ordering Information table for more details.
Figure 7-8 Timing Diagram for SMBus ALERT
TMP411-Q1 TMP411D-Q1 SMBus Alert Timing DiagramFigure 7-9 SMBus Alert Timing Diagram