SLOS877C October   2014  – April 2021 TMP451-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics for Figure 1-1
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Temperature Measurement Data
        1. 7.3.1.1 Standard Binary to Decimal Temperature Data Calculation Example
        2. 7.3.1.2 Standard Decimal to Binary Temperature Data Calculation Example
      2. 7.3.2 Series Resistance Cancellation
      3. 7.3.3 Differential Input Capacitance
      4. 7.3.4 Filtering
      5. 7.3.5 Sensor Fault
      6. 7.3.6 ALERT and THERM Functions
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Bus Overview
        2. 7.5.1.2 Bus Definitions
        3. 7.5.1.3 Serial Bus Address
        4. 7.5.1.4 Read and Write Operations
        5. 7.5.1.5 Timeout Function
        6. 7.5.1.6 High-Speed Mode
    6. 7.6 Register Map
      1. 7.6.1 Register Information
        1. 7.6.1.1  Pointer Register
        2. 7.6.1.2  Temperature Registers
        3. 7.6.1.3  Status Register
        4. 7.6.1.4  Configuration Register
        5. 7.6.1.5  Conversion Rate Register
        6. 7.6.1.6  One-Shot Start Register
        7. 7.6.1.7  η-Factor Correction Register
        8. 7.6.1.8  Offset Register
        9. 7.6.1.9  General Call Reset
        10. 7.6.1.10 Identification Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1.2 Bus Definitions

The TMP451-Q1 device is two-wire and SMBus-compatible. Figure 7-4 and Figure 7-5 show the timing for various operations on the TMP451-Q1 device. The bus definitions are as follows:

    Bus Idle:Both SDA and SCL lines remain high.
    Start Data Transfer:A change in the state of the SDA line, from high to low, while the SCL line is high, defines a start condition. Each data transfer initiates with a start condition.
    Stop Data Transfer:A change in the state of the SDA line from low to high while the SCL line is high defines a stop condition. Each data transfer terminates with a repeated start or stop condition.
    Data Transfer:The number of data bytes transferred between a start and a stop condition is not limited and is determined by the master device. The receiver acknowledges data transfer.
    Acknowledge:Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Take setup and hold times into account. On a master receive, data transfer termination can be signaled by the master generating a not-acknowledge on the last byte that has been transmitted by the slave.
GUID-A50BAB94-CCBA-4E63-A73B-03111DFE91B4-low.gif
Slave address 1001100 shown.
Figure 7-4 Two-Wire Timing Diagram for Write Word Format
GUID-B2011698-E39A-45FE-B712-0E7AB582A57B-low.gif
Slave address 1001100 shown.
Master should leave SDA high to terminate a single-byte read operation.
Figure 7-5 Two-Wire Timing Diagram for Single-Byte Read Format