SNIS210G April   2019  – November 2023 TMP61-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TMP61-Q1 R-T table
      2. 7.3.2 Linear Resistance Curve
      3. 7.3.3 Positive Temperature Coefficient (PTC)
      4. 7.3.4 Built-In Fail Safe
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 AEC-Q200 Qualifications
    3. 8.3 Typical Application
      1. 8.3.1 Thermistor Biasing Circuits
        1. 8.3.1.1 Design Requirements
        2. 8.3.1.2 Detailed Design Procedure
          1. 8.3.1.2.1 Thermal Protection With Comparator
          2. 8.3.1.2.2 Thermal Foldback
        3. 8.3.1.3 Application Curve
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Glossary
    6. 9.6 Electrostatic Discharge Caution
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The TMP61-Q1 silicon linear thermistor has a linear positive temperature coefficient (PTC) that results in a uniform and consistent temperature coefficient resistance (TCR) across a wide operating temperature range. TI uses a special silicon process where the doping level and active region areas devices control the key characteristics (the temperature coefficient resistance (TCR) and nominal resistance (R25)). The device has an active area and a substrate due to the polarized terminals. Connect the positive terminal to the highest voltage potential. Connect the negative terminal to the lowest voltage potential.

Unlike an NTC, which is a purely resistive device, the TMP61-Q1 resistance is affected by the current across the device and the resistance changes when the temperature changes. In a voltage divider circuit, TI recommends to maintain the top resistor value at 10 kΩ. Changing the top resistor value or the VBIAS value changes the resistance vs temperature table (R-T table) of the TMP61-Q1, and subsequently the polynomials as described in the Design Requirements section. Consult the TMP61-Q1 R-T table section for more information.

Equation 1 can help the user approximate the TCR.

Equation 1. GUID-DB56B39F-978F-4FC3-9175-A3A17D58AB82-low.gif

where

  • TCR is in ppm/°C

Key terms and definitions:

  • ISNS: Current flowing through the TMP61-Q1 device
  • VSNS: Voltage across the two TMP61-Q1 terminal
  • IBIAS: Current supplied by the biasing circuit.
  • VBIAS: Voltage supplied by the biasing circuit.
  • VTEMP: Output voltage that corresponds to the measured temperature. Note that this is different from VSNS. In the use case of a voltage divider circuit with the TMP61-Q1 in the high side, VTEMP is measured across RBIAS.