SNIS220B March   2020  – November 2020 TMP64-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TMP64-Q1 R-T table
      2. 8.3.2 Linear resistance curve
      3. 8.3.3 Positive Temperature Coefficient (PTC)
      4. 8.3.4 Built-In Fail Safe
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Thermistor Biasing Circuits
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Thermal Protection With Comparator
          2. 9.2.1.2.2 Thermal Foldback
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Overview

The TMP64-Q1 silicon linear thermistor has a linear positive temperature coefficient (PTC) that results in a uniform and consistent temperature coefficient resistance (TCR) across a wide operating temperature range. TI uses a special silicon process where the the doping level and active region areas devices control the key characteristics (the temperature coefficient resistance (TCR) and nominal resistance (R25)) . The device has an active area and a substrate due to the polarized terminals. Connect the positive terminal to the highest voltage potential. Connect the negative terminal to the lowest voltage potential.

Unlike an NTC, which is a purely resistive device, the TMP64-Q1 resistance is affected by the current across the device and the resistance changes when the temperature changes. In a voltage divider circuit, it is recommended to maintain the top resistor value at 47 kΩ. Changing the top resistor value or the VBIAS value changes the resistance vs temperature table (R-T table) of the TMP64-Q1, and subsequently the polynomials as described in Section 9.2.1.1. Consult Section 8.3.1 for more information.

Equation 1. TCR (ppm/°C) = (RT2 – RT1) / ((T2 – T1) × R(T2+T1)/2)

Below are the definitions of the key terms used throughout this document:

  • ISNS: Current flowing through the TMP64-Q1.
  • VSNS: Voltage across the two TMP64-Q1 terminals.
  • IBias: Current supplied by the biasing circuit.
  • VBias: Voltage supplied by the biasing circuit.
  • VTemp: Output voltage that corresponds to the measured temperature. Note that this is different from VSns. In the use case of a voltage divider circuit with the TMP64-Q1 in the high side, VTemp is taken across RBias.