6.5.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non power-on reset. Setting any of these bits blocks reset to all PLLCTL registers in order to maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting module specific bit in RSISO, the corresponding MDCTLx[12] bit also must be set in PSC to reset-isolate a particular module. For more information on MDCTLx Register, see the Power Sleep Controller (PSC) for KeyStone Devices User's Guide. The Reset Isolation Register (RSISO) is shown in Figure 6-12 and described in Table 6-18.
Figure 6-12 Reset Isolation Register (RSISO)
Reserved |
Reserved |
SRISO |
Reserved |
Legend: R = Read only; R/W = Read/Write; -n = value after reset |
Table 6-18 Reset Isolation Register (RSISO) Field Descriptions
BIT |
FIELD |
DESCRIPTION |
31-10 |
Reserved |
Reserved. |
9 |
Reserved |
Reserved. |
8 |
SRISO |
Isolate SmartReflex
- 0 = Not reset isolated
- 1 = Reset Isolated
|
7-0 |
Reserved |
Reserved. |