Refer to the PDF data sheet for device specific package drawings
IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 8-14 and described in Table 8-16.
|SRCC23 – SRCC4||SRCC3||SRCC2||SRCC1||SRCC0||Reserved|
|RW +0||RW +0||RW +0||RW +0||RW +0 (per bit field)||RW +0||RW +0||RW +0||RW +0||R, +0000|
|Legend: R = Read only; RW = Read/Write; -n = value after reset|
|31-4||SRCCx||Interrupt source acknowledgement.
Reads return current value of internal register bit.