SPRS377F September   2008  – June 2014 TMS320C6745 , TMS320C6747

PRODUCTION DATA.  

  1. 1TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6747 Top Level Memory Map
      2. Table 3-5 C6745 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.6.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.6.5  External Memory Interface B (only SDRAM)
      6. 3.6.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.6.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.6.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.6.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.6.10 Boot
      11. 3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.6.12 Inter-Integrated Circuit Modules (I2C0, I2C1)
      13. 3.6.13 Timers
      14. 3.6.14 Universal Host-Port Interface (UHPI)
      15. 3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.6.16 Universal Serial Bus Modules (USB0, USB1)
      17. 3.6.17 Ethernet Media Access Controller (EMAC)
      18. 3.6.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.6.19 Liquid Crystal Display Controller (LCD)
      20. 3.6.20 General Purpose Input Output (GPIO)
      21. 3.6.21 Reserved and No Connect
      22. 3.6.22 Supply and Ground
      23. 3.6.23 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-on Sequence
      2. 6.3.2 Power-off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-9  Timing Requirements for GPIO Inputs (see )
        2. Table 6-10 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-11 Timing Requirements for External Interrupts (see )
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface A (EMIFA) Registers
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 EMIFA SDRAM Interface Timing Requirements
        2. Table 6-20 EMIFA SDRAM Interface Switching Characteristics
        3. Table 6-21 EMIFA Asynchronous Memory Timing Requirements
        4. Table 6-22 EMIFA Asynchronous Memory Switching Characteristics
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Electrical Data/Timing
        1. Table 6-26 EMIFB SDRAM Interface Timing Requirements
        2. Table 6-27 EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature Range
        3. Table 6-28 EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive Temperature Ranges
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-32 Timing Requirements for MMC/SD Module (see and )
        2. Table 6-33 Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see through )
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Registers
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-41 Timing Requirements for MDIO Input (see and )
        2. Table 6-42 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-47 McASP0 Timing Requirements
          2. Table 6-48 McASP0 Switching Characteristics
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
          1. Table 6-49 McASP1 Timing Requirements
          2. Table 6-50 McASP1 Switching Characteristics
        3. 6.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
          1. Table 6-51 McASP2 Timing Requirements
          2. Table 6-52 McASP2 Switching Characteristics
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-54 General Timing Requirements for SPI0 Master Modes
          2. Table 6-55 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-56 Additional SPI0 Master Timings, 4-Pin Enable Option
          4. Table 6-57 Additional SPI0 Master Timings, 4-Pin Chip Select Option
          5. Table 6-58 Additional SPI0 Master Timings, 5-Pin Option
          6. Table 6-59 Additional SPI0 Slave Timings, 4-Pin Enable Option
          7. Table 6-60 Additional SPI0 Slave Timings, 4-Pin Chip Select Option
          8. Table 6-61 Additional SPI0 Slave Timings, 5-Pin Option
          9. Table 6-62 General Timing Requirements for SPI1 Master Modes
          10. Table 6-63 General Timing Requirements for SPI1 Slave Modes
          11. Table 6-64 Additional SPI1 Master Timings, 4-Pin Enable Option
          12. Table 6-65 Additional SPI1 Master Timings, 4-Pin Chip Select Option
          13. Table 6-66 Additional SPI1 Master Timings, 5-Pin Option
          14. Table 6-67 Additional SPI1 Slave Timings, 4-Pin Enable Option
          15. Table 6-68 Additional SPI1 Slave Timings, 4-Pin Chip Select Option
          16. Table 6-69 Additional SPI1 Slave Timings, 5-Pin Option
    18. 6.18 Enhanced Capture (eCAP) Peripheral
      1. Table 6-71 Enhanced Capture (eCAP) Timing Requirement
      2. Table 6-72 eCAP Switching Characteristics
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
      1. Table 6-74 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
      2. Table 6-75 eQEP Switching Characteristics
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-77 eHRPWM Timing Requirements
        2. Table 6-78 eHRPWM Switching Characteristics
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 LCD Controller
      1. 6.21.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.21.2 LCD Raster Mode
        1. Table 6-84 LCD Raster Mode Timing
    22. 6.22 Timers
      1. 6.22.1 Timer Electrical Data/Timing
        1. Table 6-86 Timing Requirements for Timer Input (see )
        2. Table 6-87 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    23. 6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.23.1 I2C Device-Specific Information
      2. 6.23.2 I2C Peripheral Registers Description(s)
      3. 6.23.3 I2C Electrical Data/Timing
        1. 6.23.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-89 I2C Input Timing Requirements
          2. Table 6-90 I2C Switching Characteristics
    24. 6.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.24.1 UART Peripheral Registers Description(s)
      2. 6.24.2 UART Electrical Data/Timing
        1. Table 6-92 Timing Requirements for UARTx Receive (see )
        2. Table 6-93 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    25. 6.25 USB1 Host Controller Registers (USB1.1 OHCI)
      1. Table 6-95 Switching Characteristics Over Recommended Operating Conditions for USB1
      2. 6.25.1     USB1 Unused Signal Configuration
    26. 6.26 USB0 OTG (USB2.0 OTG)
      1. 6.26.1 USB2.0 Electrical Data/Timing
        1. Table 6-97 Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see )
      2. 6.26.2 USB0 Unused Signal Configuration
    27. 6.27 Host-Port Interface (UHPI)
      1. 6.27.1 HPI Device-Specific Information
      2. 6.27.2 HPI Peripheral Register Description(s)
      3. 6.27.3 HPI Electrical Data/Timing
        1. Table 6-99  Timing Requirements for Host-Port Interface Cycles
        2. Table 6-100 Switching Characteristics for Host-Port Interface Cycles
    28. 6.28 Power and Sleep Controller (PSC)
      1. 6.28.1 Power Domain and Module Topology
        1. 6.28.1.1 Power Domain States
        2. 6.28.1.2 Module States
    29. 6.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.29.1 PRUSS Register Descriptions
    30. 6.30 Emulation Logic
      1. 6.30.1 JTAG Port Description
      2. 6.30.2 Scan Chain Configuration Parameters
      3. 6.30.3 JTAG 1149.1 Boundary Scan Considerations
    31. 6.31 IEEE 1149.1 JTAG
      1. 6.31.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
      2. 6.31.2 JTAG Test-Port Electrical Data/Timing
        1. Table 6-115 Timing Requirements for JTAG Test Port (see )
        2. Table 6-116 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
    32. 6.32 Real Time Clock (RTC)
      1. 6.32.1 Clock Source
      2. 6.32.2 Real-Time Clock Registers
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Support Resources
    4. 7.4 Related Links
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZKB
    2. 8.2 Thermal Data for PTP
    3. 8.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.3.1 Standoff Height
      2. 8.3.2 PowerPAD™ PCB Footprint
    4. 8.4 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.16.1 McASP Peripheral Registers Description(s)

Registers for the McASP are summarized in Table 6-44. The registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 6-45

Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-46. Note that the AFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control registers are accessed through the peripheral configuration port.

Table 6-44 McASP Registers Accessed Through Peripheral Configuration Port

McASP0
BYTE
ADDRESS		 McASP1
BYTE
ADDRESS		 McASP2
BYTE
ADDRESS		 ACRONYM REGISTER DESCRIPTION
0x01D0 0000 0x01D0 4000 0x01D0 8000 REV Revision identification register
0x01D0 0010 0x01D0 4010 0x01D0 8010 PFUNC Pin function register
0x01D0 0014 0x01D0 4014 0x01D0 8014 PDIR Pin direction register
0x01D0 0018 0x01D0 4018 0x01D0 8018 PDOUT Pin data output register
0x01D0 001C 0x01D0 401C 0x01D0 801C PDIN Read returns: Pin data input register
0x01D0 001C 0x01D0 401C 0x01D0 801C PDSET Writes affect: Pin data set register
(alternate write address: PDOUT)
0x01D0 0020 0x01D0 4020 0x01D0 8020 PDCLR Pin data clear register (alternate write address: PDOUT)
0x01D0 0044 0x01D0 4044 0x01D0 8044 GBLCTL Global control register
0x01D0 0048 0x01D0 4048 0x01D0 8048 AMUTE Audio mute control register
0x01D0 004C 0x01D0 404C 0x01D0 804C DLBCTL Digital loopback control register
0x01D0 0050 0x01D0 4050 0x01D0 8050 DITCTL DIT mode control register
0x01D0 0060 0x01D0 4060 0x01D0 8060 RGBLCTL Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows receiver to be reset independently from transmitter
0x01D0 0064 0x01D0 4064 0x01D0 8064 RMASK Receive format unit bit mask register
0x01D0 0068 0x01D0 4068 0x01D0 8068 RFMT Receive bit stream format register
0x01D0 006C 0x01D0 406C 0x01D0 806C AFSRCTL Receive frame sync control register
0x01D0 0070 0x01D0 4070 0x01D0 8070 ACLKRCTL Receive clock control register
0x01D0 0074 0x01D0 4074 0x01D0 8074 AHCLKRCTL Receive high-frequency clock control register
0x01D0 0078 0x01D0 4078 0x01D0 8078 RTDM Receive TDM time slot 0-31 register
0x01D0 007C 0x01D0 407C 0x01D0 807C RINTCTL Receiver interrupt control register
0x01D0 0080 0x01D0 4080 0x01D0 8080 RSTAT Receiver status register
0x01D0 0084 0x01D0 4084 0x01D0 8084 RSLOT Current receive TDM time slot register
0x01D0 0088 0x01D0 4088 0x01D0 8088 RCLKCHK Receive clock check control register
0x01D0 008C 0x01D0 408C 0x01D0 808C REVTCTL Receiver DMA event control register
0x01D0 00A0 0x01D0 40A0 0x01D0 80A0 XGBLCTL Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows transmitter to be reset independently from receiver
0x01D0 00A4 0x01D0 40A4 0x01D0 80A4 XMASK Transmit format unit bit mask register
0x01D0 00A8 0x01D0 40A8 0x01D0 80A8 XFMT Transmit bit stream format register
0x01D0 00AC 0x01D0 40AC 0x01D0 80AC AFSXCTL Transmit frame sync control register
0x01D0 00B0 0x01D0 40B0 0x01D0 80B0 ACLKXCTL Transmit clock control register
0x01D0 00B4 0x01D0 40B4 0x01D0 80B4 AHCLKXCTL Transmit high-frequency clock control register
0x01D0 00B8 0x01D0 40B8 0x01D0 80B8 XTDM Transmit TDM time slot 0-31 register
0x01D0 00BC 0x01D0 40BC 0x01D0 80BC XINTCTL Transmitter interrupt control register
0x01D0 00C0 0x01D0 40C0 0x01D0 80C0 XSTAT Transmitter status register
0x01D0 00C4 0x01D0 40C4 0x01D0 80C4 XSLOT Current transmit TDM time slot register
0x01D0 00C8 0x01D0 40C8 0x01D0 80C8 XCLKCHK Transmit clock check control register
0x01D0 00CC 0x01D0 40CC 0x01D0 80CC XEVTCTL Transmitter DMA event control register
0x01D0 0100 0x01D0 4100 0x01D0 8100 DITCSRA0 Left (even TDM time slot) channel status register (DIT mode) 0
0x01D0 0104 0x01D0 4104 0x01D0 8104 DITCSRA1 Left (even TDM time slot) channel status register (DIT mode) 1
0x01D0 0108 0x01D0 4108 0x01D0 8108 DITCSRA2 Left (even TDM time slot) channel status register (DIT mode) 2
0x01D0 010C 0x01D0 410C 0x01D0 810C DITCSRA3 Left (even TDM time slot) channel status register (DIT mode) 3
0x01D0 0110 0x01D0 4110 0x01D0 8110 DITCSRA4 Left (even TDM time slot) channel status register (DIT mode) 4
0x01D0 0114 0x01D0 4114 0x01D0 8114 DITCSRA5 Left (even TDM time slot) channel status register (DIT mode) 5
0x01D0 0118 0x01D0 4118 0x01D0 8118 DITCSRB0 Right (odd TDM time slot) channel status register (DIT mode) 0
0x01D0 011C 0x01D0 411C 0x01D0 811C DITCSRB1 Right (odd TDM time slot) channel status register (DIT mode) 1
0x01D0 0120 0x01D0 4120 0x01D0 8120 DITCSRB2 Right (odd TDM time slot) channel status register (DIT mode) 2
0x01D0 0124 0x01D0 4124 0x01D0 8124 DITCSRB3 Right (odd TDM time slot) channel status register (DIT mode) 3
0x01D0 0128 0x01D0 4128 0x01D0 8128 DITCSRB4 Right (odd TDM time slot) channel status register (DIT mode) 4
0x01D0 012C 0x01D0 412C 0x01D0 812C DITCSRB5 Right (odd TDM time slot) channel status register (DIT mode) 5
0x01D0 0130 0x01D0 4130 0x01D0 8130 DITUDRA0 Left (even TDM time slot) channel user data register (DIT mode) 0
0x01D0 0134 0x01D0 4134 0x01D0 8134 DITUDRA1 Left (even TDM time slot) channel user data register (DIT mode) 1
0x01D0 0138 0x01D0 4138 0x01D0 8138 DITUDRA2 Left (even TDM time slot) channel user data register (DIT mode) 2
0x01D0 013C 0x01D0 413C 0x01D0 813C DITUDRA3 Left (even TDM time slot) channel user data register (DIT mode) 3
0x01D0 0140 0x01D0 4140 0x01D0 8140 DITUDRA4 Left (even TDM time slot) channel user data register (DIT mode) 4
0x01D0 0144 0x01D0 4144 0x01D0 8144 DITUDRA5 Left (even TDM time slot) channel user data register (DIT mode) 5
0x01D0 0148 0x01D0 4148 0x01D0 8148 DITUDRB0 Right (odd TDM time slot) channel user data register (DIT mode) 0
0x01D0 014C 0x01D0 414C 0x01D0 814C DITUDRB1 Right (odd TDM time slot) channel user data register (DIT mode) 1
0x01D0 0150 0x01D0 4150 0x01D0 8150 DITUDRB2 Right (odd TDM time slot) channel user data register (DIT mode) 2
0x01D0 0154 0x01D0 4154 0x01D0 8154 DITUDRB3 Right (odd TDM time slot) channel user data register (DIT mode) 3
0x01D0 0158 0x01D0 4158 0x01D0 8158 DITUDRB4 Right (odd TDM time slot) channel user data register (DIT mode) 4
0x01D0 015C 0x01D0 415C 0x01D0 815C DITUDRB5 Right (odd TDM time slot) channel user data register (DIT mode) 5
0x01D0 0180 0x01D0 4180 0x01D0 8180 SRCTL0 Serializer control register 0
0x01D0 0184 0x01D0 4184 0x01D0 8184 SRCTL1 Serializer control register 1
0x01D0 0188 0x01D0 4188 0x01D0 8188 SRCTL2 Serializer control register 2
0x01D0 018C 0x01D0 418C 0x01D0 818C SRCTL3 Serializer control register 3
0x01D0 0190 0x01D0 4190 0x01D0 8190 SRCTL4 Serializer control register 4
0x01D0 0194 0x01D0 4194 0x01D0 8194 SRCTL5 Serializer control register 5
0x01D0 0198 0x01D0 4198 0x01D0 8198 SRCTL6 Serializer control register 6
0x01D0 019C 0x01D0 419C 0x01D0 819C SRCTL7 Serializer control register 7
0x01D0 01A0 0x01D0 41A0 0x01D0 81A0 SRCTL8 Serializer control register 8
0x01D0 01A4 0x01D0 41A4 0x01D0 81A4 SRCTL9 Serializer control register 9
0x01D0 01A8 0x01D0 41A8 0x01D0 81A8 SRCTL10 Serializer control register 10
0x01D0 01AC 0x01D0 41AC 0x01D0 81AC SRCTL11 Serializer control register 11
0x01D0 01B0 0x01D0 41B0 0x01D0 81B0 SRCTL12 Serializer control register 12
0x01D0 01B4 0x01D0 41B4 0x01D0 81B4 SRCTL13 Serializer control register 13
0x01D0 01B8 0x01D0 41B8 0x01D0 81B8 SRCTL14 Serializer control register 14
0x01D0 01BC 0x01D0 41BC 0x01D0 81BC SRCTL15 Serializer control register 15
0x01D0 0200 0x01D0 4200 0x01D0 8200 XBUF0(1) Transmit buffer register for serializer 0
0x01D0 0204 0x01D0 4204 0x01D0 8204 XBUF1(1) Transmit buffer register for serializer 1
0x01D0 0208 0x01D0 4208 0x01D0 8208 XBUF2(1) Transmit buffer register for serializer 2
0x01D0 020C 0x01D0 420C 0x01D0 820C XBUF3(1) Transmit buffer register for serializer 3
0x01D0 0210 0x01D0 4210 0x01D0 8210 XBUF4(1) Transmit buffer register for serializer 4
0x01D0 0214 0x01D0 4214 0x01D0 8214 XBUF5(1) Transmit buffer register for serializer 5
0x01D0 0218 0x01D0 4218 0x01D0 8218 XBUF6(1) Transmit buffer register for serializer 6
0x01D0 021C 0x01D0 421C 0x01D0 821C XBUF7(1) Transmit buffer register for serializer 7
0x01D0 0220 0x01D0 4220 0x01D0 8220 XBUF8(1) Transmit buffer register for serializer 8
0x01D0 0224 0x01D0 4224 0x01D0 8224 XBUF9(1) Transmit buffer register for serializer 9
0x01D0 0228 0x01D0 4228 0x01D0 8228 XBUF10(1) Transmit buffer register for serializer 10
0x01D0 022C 0x01D0 422C 0x01D0 822C XBUF11(1) Transmit buffer register for serializer 11
0x01D0 0230 0x01D0 4230 0x01D0 8230 XBUF12(1) Transmit buffer register for serializer 12
0x01D0 0234 0x01D0 4234 0x01D0 8234 XBUF13(1) Transmit buffer register for serializer 13
0x01D0 0238 0x01D0 4238 0x01D0 8238 XBUF14(1) Transmit buffer register for serializer 14
0x01D0 023C 0x01D0 423C 0x01D0 823C XBUF15(1) Transmit buffer register for serializer 15
0x01D0 0280 0x01D0 4280 0x01D0 8280 RBUF0(2) Receive buffer register for serializer 0
0x01D0 0284 0x01D0 4284 0x01D0 8284 RBUF1(2) Receive buffer register for serializer 1
0x01D0 0288 0x01D0 4288 0x01D0 8288 RBUF2(2) Receive buffer register for serializer 2
0x01D0 028C 0x01D0 428C 0x01D0 828C RBUF3(2) Receive buffer register for serializer 3
0x01D0 0290 0x01D0 4290 0x01D0 8290 RBUF4(2) Receive buffer register for serializer 4
0x01D0 0294 0x01D0 4294 0x01D0 8294 RBUF5(2) Receive buffer register for serializer 5
0x01D0 0298 0x01D0 4298 0x01D0 8298 RBUF6(2) Receive buffer register for serializer 6
0x01D0 029C 0x01D0 429C 0x01D0 829C RBUF7(2) Receive buffer register for serializer 7
0x01D0 02A0 0x01D0 42A0 0x01D0 82A0 RBUF8(2) Receive buffer register for serializer 8
0x01D0 02A4 0x01D0 42A4 0x01D0 82A4 RBUF9(2) Receive buffer register for serializer 9
0x01D0 02A8 0x01D0 42A8 0x01D0 82A8 RBUF10(2) Receive buffer register for serializer 10
0x01D0 02AC 0x01D0 42AC 0x01D0 82AC RBUF11(2) Receive buffer register for serializer 11
0x01D0 02B0 0x01D0 42B0 0x01D0 82B0 RBUF12(2) Receive buffer register for serializer 12
0x01D0 02B4 0x01D0 42B4 0x01D0 82B4 RBUF13(2) Receive buffer register for serializer 13
0x01D0 02B8 0x01D0 42B8 0x01D0 82BB RBUF14(2) Receive buffer register for serializer 14
0x01D0 02BC 0x01D0 42BC 0x01D0 82BC RBUF15(2) Receive buffer register for serializer 15
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.

Table 6-45 McASP Registers Accessed Through DMA Port

Hex Address Register
Name		 McASP0
BYTE ADDRESS		 McASP1
BYTE ADDRESS		 McASP2
BYTE ADDRESS		 REGISTER DESCRIPTION
Read Accesses RBUF 01D0 2000 01D0 6000 01D0 A000 Receive buffer DMA port address. Cycles through receive serializers, skipping over transmit serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Reads from DMA port only if RBUSEL = 0 in RFMT.
Write Accesses XBUF 01D0 2000 01D0 6000 01D0 A000 Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA port only if XBUSEL = 0 in XFMT.

Table 6-46 McASP AFIFO Registers Accessed Through Peripheral Configuration Port

McASP0
BYTE ADDRESS		 McASP1
BYTE ADDRESS		 McASP2
BYTE ADDRESS		 ACRONYM REGISTER DESCRIPTION
0x01D0 1000 0x01D0 5000 0x01D0 9000 AFIFOREV AFIFO revision identification register
0x01D0 1010 0x01D0 5010 0x01D0 9010 WFIFOCTL Write FIFO control register
0x01D0 1014 0x01D0 5014 0x01D0 9014 WFIFOSTS Write FIFO status register
0x01D0 1018 0x01D0 5018 0x01D0 9018 RFIFOCTL Read FIFO control register
0x01D0 101C 0x01D0 501C 0x01D0 901C RFIFOSTS Read FIFO status register