SPRSP45B March   2020  – December 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pin Multiplexing
      1. 6.4.1 GPIO Muxed Pins
        1. 6.4.1.1 GPIO Muxed Pins Table
      2. 6.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 6.4.3 GPIO Input X-BAR
      4. 6.4.4 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 6.5 Pins With Internal Pullup and Pulldown
    6. 6.6 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5.     Supply Voltages
    6. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption
      2. 7.5.2 Operating Mode Test Description
      3. 7.5.3 Current Consumption Graphs
      4. 7.5.4 Reducing Current Consumption
        1. 7.5.4.1 Typical Current Reduction per Disabled Peripheral
    7. 7.6  Electrical Characteristics
    8. 7.7  Thermal Resistance Characteristics for PN Package
    9. 7.8  Thermal Resistance Characteristics for PM Package
    10. 7.9  Thermal Resistance Characteristics for PT Package
    11. 7.10 Thermal Design Considerations
    12. 7.11 System
      1. 7.11.1 Power Management
        1. 7.11.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 7.11.1.2 Power Sequencing
        3. 7.11.1.3 Power-On Reset (POR)
        4. 7.11.1.4 Brownout Reset (BOR)
      2. 7.11.2 Reset Timing
        1. 7.11.2.1 Reset Sources
        2. 7.11.2.2 Reset Electrical Data and Timing
          1. 7.11.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.11.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.11.2.2.3 Reset Timing Diagrams
      3. 7.11.3 Clock Specifications
        1. 7.11.3.1 Clock Sources
        2. 7.11.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.11.3.2.1.1 Input Clock Frequency
            2. 7.11.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.11.3.2.1.3 X1 Timing Requirements
            4. 7.11.3.2.1.4 APLL Characteristics
            5. 7.11.3.2.1.5 XCLKOUT Switching Characteristics
            6. 7.11.3.2.1.6 Internal Clock Frequencies
        3. 7.11.3.3 Input Clocks and PLLs
        4. 7.11.3.4 Crystal Oscillator
          1. 7.11.3.4.1 Crystal Oscillator Parameters
          2. 7.11.3.4.2 Crystal Oscillator Electrical Characteristics
        5. 7.11.3.5 Internal Oscillators
          1. 7.11.3.5.1 INTOSC Characteristics
      4. 7.11.4 Flash Parameters
      5. 7.11.5 Emulation/JTAG
        1. 7.11.5.1 JTAG Electrical Data and Timing
          1. 7.11.5.1.1 JTAG Timing Requirements
          2. 7.11.5.1.2 JTAG Switching Characteristics
          3. 7.11.5.1.3 JTAG Timing Diagram
        2. 7.11.5.2 cJTAG Electrical Data and Timing
          1. 7.11.5.2.1 cJTAG Timing Requirements
          2. 7.11.5.2.2 cJTAG Switching Characteristics
          3. 7.11.5.2.3 cJTAG Timing Diagram
      6. 7.11.6 GPIO Electrical Data and Timing
        1. 7.11.6.1 GPIO – Output Timing
          1. 7.11.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.11.6.2 GPIO – Input Timing
          1. 7.11.6.2.1 General-Purpose Input Timing Requirements
          2. 7.11.6.2.2 Sampling Mode
        3. 7.11.6.3 Sampling Window Width for Input Signals
      7. 7.11.7 Interrupts
        1. 7.11.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.11.7.1.1 External Interrupt Timing Requirements
          2. 7.11.7.1.2 External Interrupt Switching Characteristics
          3. 7.11.7.1.3 External Interrupt Timing
      8. 7.11.8 Low-Power Modes
        1. 7.11.8.1 Clock-Gating Low-Power Modes
        2. 7.11.8.2 Low-Power Mode Wake-up Timing
          1. 7.11.8.2.1 IDLE Mode Timing Requirements
          2. 7.11.8.2.2 IDLE Mode Switching Characteristics
          3. 7.11.8.2.3 IDLE Entry and Exit Timing Diagram
          4. 7.11.8.2.4 STANDBY Mode Timing Requirements
          5. 7.11.8.2.5 STANDBY Mode Switching Characteristics
          6. 7.11.8.2.6 STANDBY Entry and Exit Timing Diagram
          7. 7.11.8.2.7 HALT Mode Timing Requirements
          8. 7.11.8.2.8 HALT Mode Switching Characteristics
          9. 7.11.8.2.9 HALT Entry and Exit Timing Diagram
    13. 7.12 Analog Peripherals
      1.      Analog Pins and Internal Connections
      2.      Analog Signal Descriptions
      3. 7.12.1 Analog-to-Digital Converter (ADC)
        1. 7.12.1.1 ADC Configurability
          1. 7.12.1.1.1 Signal Mode
        2. 7.12.1.2 ADC Electrical Data and Timing
          1. 7.12.1.2.1 ADC Operating Conditions
          2. 7.12.1.2.2 ADC Characteristics
          3. 7.12.1.2.3 ADC Input Model
          4. 7.12.1.2.4 ADC Timing Diagrams
      4. 7.12.2 Temperature Sensor
        1. 7.12.2.1 Temperature Sensor Electrical Data and Timing
          1. 7.12.2.1.1 Temperature Sensor Characteristics
      5. 7.12.3 Comparator Subsystem (CMPSS)
        1. 7.12.3.1 CMPSS Electrical Data and Timing
          1. 7.12.3.1.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 7.12.3.1.2 CMPSS DAC Static Electrical Characteristics
          4. 7.12.3.1.3 CMPSS Illustrative Graphs
    14. 7.13 Control Peripherals
      1. 7.13.1 Enhanced Pulse Width Modulator (ePWM)
        1. 7.13.1.1 Control Peripherals Synchronization
        2. 7.13.1.2 ePWM Electrical Data and Timing
          1. 7.13.1.2.1 ePWM Timing Requirements
          2. 7.13.1.2.2 ePWM Switching Characteristics
          3. 7.13.1.2.3 Trip-Zone Input Timing
            1. 7.13.1.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.13.1.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.13.1.3.1 External ADC Start-of-Conversion Switching Characteristics
      2. 7.13.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.13.2.1 HRPWM Electrical Data and Timing
          1. 7.13.2.1.1 High-Resolution PWM Characteristics
      3. 7.13.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 7.13.3.1 High-Resolution Capture (HRCAP)
        2.       eCAP and HRCAP Block Diagram
        3. 7.13.3.2 eCAP/HRCAP Synchronization
        4. 7.13.3.3 eCAP Electrical Data and Timing
          1. 7.13.3.3.1 eCAP Timing Requirements
          2. 7.13.3.3.2 eCAP Switching Characteristics
        5. 7.13.3.4 HRCAP Electrical Data and Timing
          1. 7.13.3.4.1 HRCAP Switching Characteristics
          2.        HRCAP Figure and Graph
      4. 7.13.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.13.4.1 eQEP Electrical Data and Timing
          1. 7.13.4.1.1 eQEP Timing Requirements
          2. 7.13.4.1.2 eQEP Switching Characteristics
    15. 7.14 Communications Peripherals
      1. 7.14.1 Controller Area Network (CAN)
      2. 7.14.2 Inter-Integrated Circuit (I2C)
        1. 7.14.2.1 I2C Electrical Data and Timing
          1. 7.14.2.1.1 I2C Timing Requirements
          2. 7.14.2.1.2 I2C Switching Characteristics
          3. 7.14.2.1.3 I2C Timing Diagram
      3. 7.14.3 Power Management Bus (PMBus) Interface
        1. 7.14.3.1 PMBus Electrical Data and Timing
          1. 7.14.3.1.1 PMBus Electrical Characteristics
          2. 7.14.3.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.14.3.1.3 PMBus Standard Mode Switching Characteristics
      4. 7.14.4 Serial Communications Interface (SCI)
      5. 7.14.5 Serial Peripheral Interface (SPI)
        1. 7.14.5.1 SPI Master Mode Timings
          1. 7.14.5.1.1 SPI Master Mode Timing Requirements
          2. 7.14.5.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
          3. 7.14.5.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          4. 7.14.5.1.4 SPI Master Mode Timing Diagrams
        2. 7.14.5.2 SPI Slave Mode Timings
          1. 7.14.5.2.1 SPI Slave Mode Timing Requirements
          2. 7.14.5.2.2 SPI Slave Mode Switching Characteristics
          3. 7.14.5.2.3 SPI Slave Mode Timing Diagrams
      6. 7.14.6 Local Interconnect Network (LIN)
      7. 7.14.7 Fast Serial Interface (FSI)
        1. 7.14.7.1 FSI Transmitter
          1. 7.14.7.1.1 FSITX Electrical Data and Timing
            1. 7.14.7.1.1.1 FSITX Switching Characteristics
            2. 7.14.7.1.1.2 FSITX Timings
        2. 7.14.7.2 FSI Receiver
          1. 7.14.7.2.1 FSIRX Electrical Data and Timing
            1. 7.14.7.2.1.1 FSIRX Timing Requirements
            2. 7.14.7.2.1.2 FSIRX Switching Characteristics
            3. 7.14.7.2.1.3 FSIRX Timings
        3. 7.14.7.3 FSI SPI Compatibility Mode
          1. 7.14.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.14.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 7.14.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 7.14.8 Host Interface Controller (HIC)
        1. 7.14.8.1 HIC Electrical Data and Timing
          1. 7.14.8.1.1 HIC Timing Requirements
          2. 7.14.8.1.2 HIC Switching Characteristics
          3. 7.14.8.1.3 HIC Timing Diagrams
  8. Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 Memory Map
        1. 8.3.1.1 Dedicated RAM (Mx RAM)
        2. 8.3.1.2 Local Shared RAM (LSx RAM)
        3. 8.3.1.3 Global Shared RAM (GSx RAM)
      2. 8.3.2 Flash Memory Map
        1. 8.3.2.1 Addresses of Flash Sectors
      3. 8.3.3 Peripheral Registers Memory Map
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  C28x Processor
      1. 8.6.1 Floating-Point Unit (FPU)
      2. 8.6.2 Fast Integer Division Unit
      3. 8.6.3 Trigonometric Math Unit (TMU)
      4. 8.6.4 VCRC Unit
    7. 8.7  Embedded Real-Time Analysis and Diagnostic (ERAD)
    8. 8.8  Background CRC-32 (BGCRC)
    9. 8.9  Direct Memory Access (DMA)
    10. 8.10 Device Boot Modes
      1. 8.10.1 Device Boot Configurations
        1. 8.10.1.1 Configuring Boot Mode Pins
        2. 8.10.1.2 Configuring Boot Mode Table Options
      2. 8.10.2 GPIO Assignments
    11. 8.11 Dual Code Security Module
    12. 8.12 Watchdog
    13. 8.13 C28x Timers
    14. 8.14 Dual-Clock Comparator (DCC)
      1. 8.14.1 Features
      2. 8.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
    15. 8.15 Configurable Logic Block (CLB)
  9. Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Markings
    4. 10.4 Tools and Software
    5. 10.5 Documentation Support
    6. 10.6 Support Resources
    7. 10.7 Trademarks
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Addresses of Flash Sectors

Table 8-2 Addresses of Flash Sectors
PART NUMBERSECTORADDRESSECC ADDRESS
SIZESTARTENDSIZESTARTEND
OTP Sectors
All F28002xTI OTP 1K x 160x0007 00000x0007 03FF128 x 160x0107 00000x0107 007F
DCSM OTP 1K x 160x0007 80000x0007 83FF128 x 160x0107 10000x0107 107F
Bank 0 Sectors
All F28002xSector 04K x 160x0008 00000x0008 0FFF512 x 160x0108 00000x0108 01FF
Sector 14K x 160x0008 10000x0008 1FFF512 x 160x0108 02000x0108 03FF
Sector 24K x 160x0008 20000x0008 2FFF512 x 160x0108 04000x0108 05FF
Sector 34K x 160x0008 30000x0008 3FFF512 x 160x0108 06000x0108 07FF
F280025, F280023Sector 44K x 160x0008 40000x0008 4FFF512 x 160x0108 08000x0108 09FF
Sector 54K x 160x0008 50000x0008 5FFF512 x 160x0108 0A000x0108 0BFF
Sector 64K x 160x0008 60000x0008 6FFF512 x 160x0108 0C000x0108 0DFF
Sector 74K x 160x0008 70000x0008 7FFF512 x 160x0108 0E000x0108 0FFF
F280025Sector 84K x 160x0008 80000x0008 8FFF512 x 160x0108 10000x0108 11FF
Sector 94K x 160x0008 90000x0008 9FFF512 x 160x0108 12000x0108 13FF
Sector 104K x 160x0008 A0000x0008 AFFF512 x 160x0108 14000x0108 15FF
Sector 114K x 160x0008 B0000x0008 BFFF512 x 160x0108 16000x0108 17FF
Sector 124K x 160x0008 C0000x0008 CFFF512 x 160x0108 18000x0108 19FF
Sector 134K x 160x0008 D0000x0008 DFFF512 x 160x0108 1A000x0108 1BFF
Sector 144K x 160x0008 E0000x0008 EFFF512 x 160x0108 1C000x0108 1DFF
Sector 154K x 160x0008 F0000x0008 FFFF512 x 160x0108 1E000x0108 1FFF