SPRSP61C October   2021  – December 2023 TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038C-Q1 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
        1. 5.4.1.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for PZ Package
    8. 6.8  Thermal Resistance Characteristics for PN Package
    9. 6.9  Thermal Resistance Characteristics for PM Package
    10. 6.10 Thermal Resistance Characteristics for PT Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1 Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
          3.        Supply Voltages
      2. 6.12.2 Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.12.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3 Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks and PLLs
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
              1. 6.12.3.4.3.3.1 X1/X2 Precondition
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Oscillator Parameters
            2. 6.12.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.12.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4 Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5 RAM and ROM Parameters
      6. 6.12.6 Emulation/JTAG
        1. 6.12.6.1 JTAG Electrical Data and Timing
          1. 6.12.6.1.1 JTAG Timing Requirements
          2. 6.12.6.1.2 JTAG Switching Characteristics
          3. 6.12.6.1.3 JTAG Timing Diagram
        2. 6.12.6.2 cJTAG Electrical Data and Timing
          1. 6.12.6.2.1 cJTAG Timing Requirements
          2. 6.12.6.2.2 cJTAG Switching Characteristics
          3. 6.12.6.2.3 cJTAG Timing Diagram
      7. 6.12.7 GPIO Electrical Data and Timing
        1. 6.12.7.1 GPIO – Output Timing
          1. 6.12.7.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.7.1.2 General-Purpose Output Timing Diagram
        2. 6.12.7.2 GPIO – Input Timing
          1. 6.12.7.2.1 General-Purpose Input Timing Requirements
          2. 6.12.7.2.2 Sampling Mode
        3. 6.12.7.3 Sampling Window Width for Input Signals
      8. 6.12.8 Interrupts
        1. 6.12.8.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.8.1.1 External Interrupt Timing Requirements
          2. 6.12.8.1.2 External Interrupt Switching Characteristics
          3. 6.12.8.1.3 External Interrupt Timing
      9. 6.12.9 Low-Power Modes
        1. 6.12.9.1 Clock-Gating Low-Power Modes
        2. 6.12.9.2 Low-Power Mode Wake-up Timing
          1. 6.12.9.2.1 IDLE Mode Timing Requirements
          2. 6.12.9.2.2 IDLE Mode Switching Characteristics
          3. 6.12.9.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.9.2.4 STANDBY Mode Timing Requirements
          5. 6.12.9.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.9.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.9.2.7 HALT Mode Timing Requirements
          8. 6.12.9.2.8 HALT Mode Switching Characteristics
          9. 6.12.9.2.9 HALT Entry and Exit Timing Diagram
    13. 6.13 Analog Peripherals
      1. 6.13.1 Analog Pins and Internal Connections
      2. 6.13.2 Analog Signal Descriptions
      3. 6.13.3 Analog-to-Digital Converter (ADC)
        1. 6.13.3.1 ADC Configurability
          1. 6.13.3.1.1 Signal Mode
        2. 6.13.3.2 ADC Electrical Data and Timing
          1. 6.13.3.2.1 ADC Operating Conditions
          2. 6.13.3.2.2 ADC Characteristics
          3. 6.13.3.2.3 ADC Input Model
          4. 6.13.3.2.4 ADC Timing Diagrams
      4. 6.13.4 Temperature Sensor
        1. 6.13.4.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.4.1.1 Temperature Sensor Characteristics
      5. 6.13.5 Comparator Subsystem (CMPSS)
        1. 6.13.5.1 CMPSS Connectivity Diagram
        2. 6.13.5.2 Block Diagram
        3. 6.13.5.3 CMPSS Electrical Data and Timing
          1. 6.13.5.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.5.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.5.3.3 CMPSS Illustrative Graphs
          5. 6.13.5.3.4 CMPSS DAC Dynamic Error
      6. 6.13.6 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.6.1 Buffered DAC Electrical Data and Timing
          1. 6.13.6.1.1 Buffered DAC Operating Conditions
          2. 6.13.6.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 Control Peripherals
      1. 6.14.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.1.1 ePWM Electrical Data and Timing
          1. 6.14.1.1.1 ePWM Timing Requirements
          2. 6.14.1.1.2 ePWM Switching Characteristics
          3. 6.14.1.1.3 Trip-Zone Input Timing
            1. 6.14.1.1.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.1.1.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.14.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.2.1 HRPWM Electrical Data and Timing
          1. 6.14.2.1.1 High-Resolution PWM Characteristics
      3. 6.14.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.14.4 Enhanced Capture (eCAP)
        1. 6.14.4.1 eCAP and HRCAP Block Diagram
        2. 6.14.4.2 eCAP Synchronization
        3. 6.14.4.3 eCAP Electrical Data and Timing
          1. 6.14.4.3.1 eCAP Timing Requirements
          2. 6.14.4.3.2 eCAP Switching Characteristics
      5. 6.14.5 High-Resolution Capture (HRCAP)
        1. 6.14.5.1 eCAP and HRCAP Block Diagram
        2. 6.14.5.2 HRCAP Electrical Data and Timing
          1. 6.14.5.2.1 HRCAP Switching Characteristics
          2. 6.14.5.2.2 HRCAP Figure and Graph
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Timing Requirements When Using Asynchronous GPIO - ASYNC - Option
    15. 6.15 Communications Peripherals
      1. 6.15.1 Controller Area Network (CAN)
      2. 6.15.2 Modular Controller Area Network (MCAN)
      3. 6.15.3 Inter-Integrated Circuit (I2C)
        1. 6.15.3.1 I2C Electrical Data and Timing
          1. 6.15.3.1.1 I2C Timing Requirements
          2. 6.15.3.1.2 I2C Switching Characteristics
          3. 6.15.3.1.3 I2C Timing Diagram
      4. 6.15.4 Power Management Bus (PMBus) Interface
        1. 6.15.4.1 PMBus Electrical Data and Timing
          1. 6.15.4.1.1 PMBus Electrical Characteristics
          2. 6.15.4.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.4.1.3 PMBus Standard Mode Switching Characteristics
      5. 6.15.5 Serial Communications Interface (SCI)
      6. 6.15.6 Serial Peripheral Interface (SPI)
        1. 6.15.6.1 SPI Master Mode Timings
          1. 6.15.6.1.1 SPI Master Mode Timing Requirements
          2. 6.15.6.1.2 SPI Master Mode Switching Characteristics - Clock Phase  0
          3. 6.15.6.1.3 SPI Master Mode Switching Characteristics - Clock Phase  1
          4. 6.15.6.1.4 SPI Master Mode Timing Diagrams
        2. 6.15.6.2 SPI Slave Mode Timings
          1. 6.15.6.2.1 SPI Slave Mode Timing Requirements
          2. 6.15.6.2.2 SPI Slave Mode Switching Characteristics
          3. 6.15.6.2.3 SPI Slave Mode Timing Diagrams
      7. 6.15.7 Local Interconnect Network (LIN)
      8. 6.15.8 Fast Serial Interface (FSI)
        1. 6.15.8.1 FSI Transmitter
          1. 6.15.8.1.1 FSITX Electrical Data and Timing
            1. 6.15.8.1.1.1 FSITX Switching Characteristics
            2. 6.15.8.1.1.2 FSITX Timings
        2. 6.15.8.2 FSI Receiver
          1. 6.15.8.2.1 FSIRX Electrical Data and Timing
            1. 6.15.8.2.1.1 FSIRX Timing Requirements
            2. 6.15.8.2.1.2 FSIRX Switching Characteristics
            3. 6.15.8.2.1.3 FSIRX Timings
        3. 6.15.8.3 FSI SPI Compatibility Mode
          1. 6.15.8.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.8.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.8.3.1.2 FSITX SPI Signaling Mode Timings
      9. 6.15.9 Host Interface Controller (HIC)
        1. 6.15.9.1 HIC Electrical Data and Timing
          1. 6.15.9.1.1 HIC Timing Requirements
          2. 6.15.9.1.2 HIC Switching Characteristics
          3. 6.15.9.1.3 HIC Timing Diagrams
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Fast Integer Division Unit
      3. 7.6.3 Trigonometric Math Unit (TMU)
      4. 7.6.4 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Background CRC-32 (BGCRC)
    10. 7.10 Direct Memory Access (DMA)
    11. 7.11 Device Boot Modes
      1. 7.11.1 Device Boot Configurations
        1. 7.11.1.1 Configuring Boot Mode Pins
        2. 7.11.1.2 Configuring Boot Mode Table Options
      2. 7.11.2 GPIO Assignments
    12. 7.12 Security
      1. 7.12.1 Securing the Boundary of the Chip
        1. 7.12.1.1 JTAGLOCK
        2. 7.12.1.2 Zero-pin Boot
      2. 7.12.2 Dual-Zone Security
      3. 7.12.3 Disclaimer
    13. 7.13 Watchdog
    14. 7.14 C28x Timers
    15. 7.15 Dual-Clock Comparator (DCC)
      1. 7.15.1 Features
      2. 7.15.2 Mapping of DCCx Clock Source Inputs
    16. 7.16 Configurable Logic Block (CLB)
    17. 7.17 Functional Safety
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Applications and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Automotive Pump
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Automotive Pump Resources
        2. 8.3.1.2 Automotive HVAC Compressor
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 HVAC Resources
        3. 8.3.1.3 On-Board Charger (OBC)
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 OBC Resources
        4. 8.3.1.4 Servo Drive Control Module
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 Servo Drive Control Module Resources
        5. 8.3.1.5 Solar Micro Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 Solar Micro Inverter Resources
        6. 8.3.1.6 Merchant Telecom Rectifiers
          1. 8.3.1.6.1 System Block Diagram
          2. 8.3.1.6.2 Merchant Telecom Rectifiers Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4.1.1 GPIO Muxed Pins

Table 5-6 GPIO Muxed Pins
0, 4, 8, 12 1 2 3 5 6 7 9 10 11 13 14 15 ALT
GPIO0 EPWM1_A I2CA_SDA SPIA_STE FSIRXA_CLK MCAN_RX CLB_OUTPUTXBAR8 EQEP1_INDEX HIC_D7 HIC_BASESEL1
GPIO1 EPWM1_B I2CA_SCL SPIA_SOMI MCAN_TX CLB_OUTPUTXBAR7 HIC_A2 FSITXA_TDM_D1 HIC_D10
GPIO2 EPWM2_A OUTPUTXBAR1 PMBUSA_SDA SPIA_SIMO SCIA_TX FSIRXA_D1 I2CB_SDA HIC_A1 CANA_TX HIC_D9
GPIO3 EPWM2_B OUTPUTXBAR2 OUTPUTXBAR2 PMBUSA_SCL SPIA_CLK SCIA_RX FSIRXA_D0 I2CB_SCL HIC_NOE CANA_RX HIC_D4
GPIO4 EPWM3_A MCAN_TX OUTPUTXBAR3 CANA_TX SPIB_CLK EQEP2_STROBE FSIRXA_CLK CLB_OUTPUTXBAR6 HIC_BASESEL2 HIC_NWE
GPIO5 EPWM3_B OUTPUTXBAR3 MCAN_RX CANA_RX SPIA_STE FSITXA_D1 CLB_OUTPUTXBAR5 HIC_A7 HIC_D4 HIC_D15
GPIO6 EPWM4_A OUTPUTXBAR4 SYNCOUT EQEP1_A SPIB_SOMI FSITXA_D0 FSITXA_D1 HIC_NBE1 CLB_OUTPUTXBAR8 HIC_D14
GPIO7 EPWM4_B OUTPUTXBAR5 EQEP1_B SPIB_SIMO FSITXA_CLK CLB_OUTPUTXBAR2 HIC_A6 HIC_D14
GPIO8 EPWM5_A ADCSOCAO EQEP1_STROBE SCIA_TX SPIA_SIMO I2CA_SCL FSITXA_D1 CLB_OUTPUTXBAR5 HIC_A0 FSITXA_TDM_CLK HIC_D8
GPIO9 EPWM5_B SCIB_TX OUTPUTXBAR6 EQEP1_INDEX SCIA_RX SPIA_CLK FSITXA_D0 LINB_RX HIC_BASESEL0 I2CB_SCL HIC_NRDY
GPIO10 EPWM6_A ADCSOCBO EQEP1_A SCIB_TX SPIA_SOMI I2CA_SDA FSITXA_CLK LINB_TX HIC_NWE FSITXA_TDM_D0 CLB_OUTPUTXBAR4
GPIO11 EPWM6_B OUTPUTXBAR7 EQEP1_B SCIB_RX SPIA_STE FSIRXA_D1 LINB_RX EQEP2_A SPIA_SIMO HIC_D6 HIC_NBE0
GPIO12 EPWM7_A MCAN_RX EQEP1_STROBE SCIB_TX PMBUSA_CTL FSIRXA_D0 LINB_TX SPIA_CLK CANA_RX HIC_D13 HIC_INT
GPIO13 EPWM7_B MCAN_TX EQEP1_INDEX SCIB_RX PMBUSA_ALERT FSIRXA_CLK LINB_RX SPIA_SOMI CANA_TX HIC_D11 HIC_D5
GPIO14 EPWM8_A SCIB_TX I2CB_SDA OUTPUTXBAR3 PMBUSA_SDA SPIB_CLK EQEP2_A LINB_TX EPWM3_A CLB_OUTPUTXBAR7 HIC_D15
GPIO15 EPWM8_B SCIB_RX I2CB_SCL OUTPUTXBAR4 PMBUSA_SCL SPIB_STE EQEP2_B LINB_RX EPWM3_B CLB_OUTPUTXBAR6 HIC_D12
GPIO16 SPIA_SIMO OUTPUTXBAR7 EPWM5_A SCIA_TX SD1_D1 EQEP1_STROBE PMBUSA_SCL XCLKOUT EQEP2_B SPIB_SOMI HIC_D1
GPIO17 SPIA_SOMI OUTPUTXBAR8 EPWM5_B SCIA_RX SD1_C1 EQEP1_INDEX PMBUSA_SDA CANA_TX HIC_D2
GPIO18 SPIA_CLK SCIB_TX CANA_RX EPWM6_A I2CA_SCL SD1_D2 EQEP2_A PMBUSA_CTL XCLKOUT LINB_TX FSITXA_TDM_CLK HIC_INT X2
GPIO19 SPIA_STE SCIB_RX CANA_TX EPWM6_B I2CA_SDA SD1_C2 EQEP2_B PMBUSA_ALERT CLB_OUTPUTXBAR1 LINB_RX FSITXA_TDM_D0 HIC_NBE0 X1
GPIO20 EQEP1_A SPIB_SIMO SD1_D3 MCAN_TX
GPIO21 EQEP1_B SPIB_SOMI SD1_C3 MCAN_RX
GPIO22 EQEP1_STROBE SCIB_TX SPIB_CLK SD1_D4 LINA_TX CLB_OUTPUTXBAR1 LINB_TX HIC_A5 EPWM4_A HIC_D13
GPIO23 EQEP1_INDEX SCIB_RX SPIB_STE SD1_C4 LINA_RX CLB_OUTPUTXBAR3 LINB_RX HIC_A3 EPWM4_B HIC_D11
GPIO24 OUTPUTXBAR1 EQEP2_A EPWM8_A SPIB_SIMO SD2_D1 LINB_TX PMBUSA_SCL SCIA_TX ERRORSTS HIC_D3
GPIO25 OUTPUTXBAR2 EQEP2_B EQEP1_A SPIB_SOMI SD2_C1 FSITXA_D1 PMBUSA_SDA SCIA_RX HIC_BASESEL0
GPIO26 OUTPUTXBAR3 EQEP2_INDEX OUTPUTXBAR3 SPIB_CLK SD2_D2 FSITXA_D0 PMBUSA_CTL I2CA_SDA HIC_D0 HIC_A1
GPIO27 OUTPUTXBAR4 EQEP2_STROBE OUTPUTXBAR4 SPIB_STE SD2_C2 FSITXA_CLK PMBUSA_ALERT I2CA_SCL HIC_D1 HIC_A4
GPIO28 SCIA_RX EPWM7_A OUTPUTXBAR5 EQEP1_A SD2_D3 EQEP2_STROBE LINA_TX SPIB_CLK ERRORSTS I2CB_SDA HIC_NOE
GPIO29 SCIA_TX EPWM7_B OUTPUTXBAR6 EQEP1_B SD2_C3 EQEP2_INDEX LINA_RX SPIB_STE ERRORSTS I2CB_SCL HIC_NCS AUXCLKIN
GPIO30 CANA_RX SPIB_SIMO OUTPUTXBAR7 EQEP1_STROBE SD2_D4 FSIRXA_CLK MCAN_RX EPWM1_A HIC_D8
GPIO31 CANA_TX SPIB_SOMI OUTPUTXBAR8 EQEP1_INDEX SD2_C4 FSIRXA_D1 MCAN_TX EPWM1_B HIC_D10
GPIO32 I2CA_SDA SPIB_CLK EPWM8_B LINA_TX SD1_D2 FSIRXA_D0 CANA_TX PMBUSA_SDA ADCSOCBO HIC_INT
GPIO33 I2CA_SCL SPIB_STE OUTPUTXBAR4 LINA_RX SD1_C2 FSIRXA_CLK CANA_RX EQEP2_B ADCSOCAO SD1_C1 HIC_D0
GPIO34 OUTPUTXBAR1 PMBUSA_SDA HIC_NBE1 I2CB_SDA HIC_D9
GPIO35 SCIA_RX I2CA_SDA CANA_RX PMBUSA_SCL LINA_RX EQEP1_A PMBUSA_CTL EPWM5_B SD2_C1 HIC_NWE TDI
GPIO37 OUTPUTXBAR2 I2CA_SCL SCIA_TX CANA_TX LINA_TX EQEP1_B PMBUSA_ALERT HIC_NRDY TDO
GPIO39 MCAN_RX FSIRXA_CLK EQEP2_INDEX CLB_OUTPUTXBAR2 SYNCOUT EQEP1_INDEX HIC_D7
GPIO40 SPIB_SIMO EPWM2_B PMBUSA_SDA FSIRXA_D0 SCIB_TX EQEP1_A LINB_TX HIC_NBE1 HIC_D5
GPIO41 EPWM2_A PMBUSA_SCL FSIRXA_D1 SCIB_RX EQEP1_B LINB_RX HIC_A4 SPIB_SOMI HIC_D12
GPIO42 LINA_RX OUTPUTXBAR5 PMBUSA_CTL I2CA_SDA EQEP1_STROBE CLB_OUTPUTXBAR3 HIC_D2 HIC_A6
GPIO43 OUTPUTXBAR6 PMBUSA_ALERT I2CA_SCL PMBUSA_ALERT EQEP1_INDEX CLB_OUTPUTXBAR4 SD2_D3 HIC_D3 HIC_A7
GPIO44 OUTPUTXBAR7 EQEP1_A PMBUSA_SDA FSITXA_CLK PMBUSA_CTL CLB_OUTPUTXBAR3 FSIRXA_D0 HIC_D7 LINB_TX HIC_D5
GPIO45 OUTPUTXBAR8 FSITXA_D0 PMBUSA_ALERT CLB_OUTPUTXBAR4 SD2_C3 HIC_D6
GPIO46 LINA_TX MCAN_TX FSITXA_D1 PMBUSA_SDA SD2_C4 HIC_NWE
GPIO47 LINA_RX MCAN_RX CLB_OUTPUTXBAR2 PMBUSA_SCL SD2_D4 FSITXA_TDM_CLK HIC_A6
GPIO48 OUTPUTXBAR3 CANA_TX SCIA_TX SD1_D1 PMBUSA_SDA HIC_A7
GPIO49 OUTPUTXBAR4 CANA_RX SCIA_RX SD1_C1 LINA_RX SD2_D1 FSITXA_D0 HIC_D2
GPIO50 EQEP1_A MCAN_TX SPIB_SIMO SD1_D2 I2CB_SDA SD2_D2 FSITXA_D1 HIC_D3
GPIO51 EQEP1_B MCAN_RX SPIB_SOMI SD1_C2 I2CB_SCL SD2_D3 FSITXA_CLK HIC_D6
GPIO52 EQEP1_STROBE CLB_OUTPUTXBAR5 SPIB_CLK SD1_D3 SYNCOUT SD2_D4 FSIRXA_D0 HIC_NWE
GPIO53 EQEP1_INDEX CLB_OUTPUTXBAR6 SPIB_STE SD1_C3 ADCSOCAO CANA_RX SD1_C1 FSIRXA_D1
GPIO54 SPIA_SIMO EQEP2_A OUTPUTXBAR2 SD1_D4 ADCSOCBO LINB_TX SD1_C2 FSIRXA_CLK FSITXA_TDM_D1
GPIO55 SPIA_SOMI EQEP2_B OUTPUTXBAR3 SD1_C4 ERRORSTS LINB_RX SD1_C3 HIC_A0
GPIO56 SPIA_CLK CLB_OUTPUTXBAR7 MCAN_TX EQEP2_STROBE SCIB_TX SD2_D1 SPIB_SIMO I2CA_SDA EQEP1_A SD1_C4 FSIRXA_D1 HIC_D6
GPIO57 SPIA_STE CLB_OUTPUTXBAR8 MCAN_RX EQEP2_INDEX SCIB_RX SD2_C1 SPIB_SOMI I2CA_SCL EQEP1_B FSIRXA_CLK HIC_D4
GPIO58 OUTPUTXBAR1 SPIB_CLK SD2_D2 LINA_TX CANA_TX EQEP1_STROBE SD2_C2 FSIRXA_D0 HIC_NRDY
GPIO59 OUTPUTXBAR2 SPIB_STE SD2_C2 LINA_RX CANA_RX EQEP1_INDEX SD2_C3 FSITXA_TDM_D1
GPIO60 MCAN_TX OUTPUTXBAR3 SPIB_SIMO SD2_D3 SD2_C4 HIC_A0
GPIO61 MCAN_RX OUTPUTXBAR4 SPIB_SOMI SD2_C3 CANA_RX
AIO224 SD2_D3 HIC_A3
AIO225 SD2_C2 HIC_NWE
AIO226 SD2_D4 HIC_A1
AIO227 SD1_C3 HIC_NBE0
AIO228 SD2_C1 HIC_A0
AIO229
AIO230 SD1_C4 HIC_BASESEL2
AIO231 SD1_C1 HIC_BASESEL1
AIO232 SD1_D4 HIC_BASESEL0
AIO233 SD2_D1 HIC_A4
AIO236
AIO237 SD1_D2 HIC_A6
AIO238 SD2_C3 HIC_NCS
AIO239 SD1_D1 HIC_A5
AIO240 SD2_C1 HIC_NBE1
AIO241 SD2_C1 HIC_NBE1
AIO242 SD2_D2 HIC_A2
AIO244 SD1_D3 HIC_A7
AIO245 SD1_C2 HIC_NOE
AIO247
AIO248
AIO249
AIO251
AIO252 SD2_C4
AIO253