SPRS945E January   2017  – April 2020 TMS320F280040 , TMS320F280040C , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280048 , TMS320F280048C , TMS320F280049 , TMS320F280049C

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 Analog Signals
      2. 4.3.2 Digital Signals
      3. 4.3.3 Power and Ground
      4. 4.3.4 Test, JTAG, and Reset
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 4.4.3 GPIO Input X-BAR
      4. 4.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 4.5 Pins With Internal Pullup and Pulldown
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 System Current Consumption (External Supply)
      2. Table 5-2 System Current Consumption (Internal VREG)
      3. Table 5-3 System Current Consumption (DCDC)
      4. 5.5.1     Operating Mode Test Description
      5. 5.5.2     Current Consumption Graphs
      6. 5.5.3     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PZ Package
      2. 5.7.2 PM Package
      3. 5.7.3 RSH Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  System
      1. 5.9.1 Power Management
        1. 5.9.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 5.9.1.2 Internal 1.2-V Switching Regulator (DC-DC)
          1. 5.9.1.2.1 PCB Layout and Component Guidelines
            1. Table 5-8 Recommended External Components
        3. 5.9.1.3 Deciding Between the LDO and the DC-DC
        4. 5.9.1.4 Power Sequencing
        5. 5.9.1.5 Power-On Reset (POR)
        6. 5.9.1.6 Brownout Reset (BOR)
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Sources
        2. 5.9.2.2 Reset Electrical Data and Timing
          1. Table 5-10 Reset (XRSn) Timing Requirements
          2. Table 5-11 Reset (XRSn) Switching Characteristics
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1 Clock Sources
        2. 5.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-13 Input Clock Frequency
            2. Table 5-14 XTAL Oscillator Characteristics
            3. Table 5-15 X1 Timing Requirements
            4. Table 5-16 PLL Lock Times
          2. 5.9.3.2.2 Internal Clock Frequencies
            1. Table 5-17 Internal Clock Frequencies
          3. 5.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-18 XCLKOUT Switching Characteristics
        3. 5.9.3.3 Input Clocks and PLLs
        4. 5.9.3.4 Crystal Oscillator
          1. Table 5-19 Crystal Oscillator Parameters
          2. Table 5-21 Crystal Oscillator Electrical Characteristics
        5. 5.9.3.5 Internal Oscillators
          1. Table 5-22 INTOSC Characteristics
      4. 5.9.4 Flash Parameters
      5. 5.9.5 Emulation/JTAG
        1. 5.9.5.1 JTAG Electrical Data and Timing
          1. Table 5-25 JTAG Timing Requirements
          2. Table 5-26 JTAG Switching Characteristics
        2. 5.9.5.2 cJTAG Electrical Data and Timing
          1. Table 5-27 cJTAG Timing Requirements
          2. Table 5-28 cJTAG Switching Characteristics
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO – Output Timing
          1. Table 5-29 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO – Input Timing
          1. Table 5-30 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
      7. 5.9.7 Interrupts
        1. 5.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-31 External Interrupt Timing Requirements
          2. Table 5-32 External Interrupt Switching Characteristics
      8. 5.9.8 Low-Power Modes
        1. 5.9.8.1 Clock-Gating Low-Power Modes
        2. 5.9.8.2 Low-Power Mode Wake-up Timing
          1. Table 5-34 IDLE Mode Timing Requirements
          2. Table 5-35 IDLE Mode Switching Characteristics
          3. Table 5-36 HALT Mode Timing Requirements
          4. Table 5-37 HALT Mode Switching Characteristics
    10. 5.10 Analog Peripherals
      1. 5.10.1 Analog-to-Digital Converter (ADC)
        1. 5.10.1.1 ADC Configurability
          1. 5.10.1.1.1 Signal Mode
        2. 5.10.1.2 ADC Electrical Data and Timing
          1. Table 5-41 ADC Operating Conditions
          2. Table 5-42 ADC Characteristics
          3. 5.10.1.2.1 ADC Input Model
          4. 5.10.1.2.2 ADC Timing Diagrams
      2. 5.10.2 Programmable Gain Amplifier (PGA)
        1. 5.10.2.1 PGA Electrical Data and Timing
          1. Table 5-47 PGA Operating Conditions
          2. Table 5-48 PGA Characteristics
          3. 5.10.2.1.1 PGA Typical Characteristics Graphs
      3. 5.10.3 Temperature Sensor
        1. 5.10.3.1 Temperature Sensor Electrical Data and Timing
          1. Table 5-49 Temperature Sensor Characteristics
      4. 5.10.4 Buffered Digital-to-Analog Converter (DAC)
        1. 5.10.4.1 Buffered DAC Electrical Data and Timing
          1. Table 5-50 Buffered DAC Operating Conditions
          2. Table 5-51 Buffered DAC Electrical Characteristics
          3. 5.10.4.1.1 Buffered DAC Illustrative Graphs
          4. 5.10.4.1.2 Buffered DAC Typical Characteristics Graphs
      5. 5.10.5 Comparator Subsystem (CMPSS)
        1. 5.10.5.1 CMPSS Electrical Data and Timing
          1. Table 5-52 Comparator Electrical Characteristics
          2. Table 5-53 CMPSS DAC Static Electrical Characteristics
          3. 5.10.5.1.1 CMPSS Illustrative Graphs
    11. 5.11 Control Peripherals
      1. 5.11.1 Enhanced Capture (eCAP)
        1. 5.11.1.1 eCAP Electrical Data and Timing
          1. Table 5-54 eCAP Timing Requirements
          2. Table 5-55 eCAP Switching Charcteristics
      2. 5.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
        1. 5.11.2.1 HRCAP Electrical Data and Timing
          1. Table 5-56 HRCAP Switching Characteristics
      3. 5.11.3 Enhanced Pulse Width Modulator (ePWM)
        1. 5.11.3.1 Control Peripherals Synchronization
        2. 5.11.3.2 ePWM Electrical Data and Timing
          1. Table 5-57 ePWM Timing Requirements
          2. Table 5-58 ePWM Switching Characteristics
          3. 5.11.3.2.1 Trip-Zone Input Timing
            1. Table 5-59 Trip-Zone Input Timing Requirements
        3. 5.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-60 External ADC Start-of-Conversion Switching Characteristics
      4. 5.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.11.4.1 HRPWM Electrical Data and Timing
          1. Table 5-61 High-Resolution PWM Characteristics
      5. 5.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.11.5.1 eQEP Electrical Data and Timing
          1. Table 5-62 eQEP Timing Requirements
          2. Table 5-63 eQEP Switching Characteristics
      6. 5.11.6 Sigma-Delta Filter Module (SDFM)
        1. 5.11.6.1 SDFM Electrical Data and Timing
          1. Table 5-64 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 5.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
          1. Table 5-65 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
    12. 5.12 Communications Peripherals
      1. 5.12.1 Controller Area Network (CAN)
      2. 5.12.2 Inter-Integrated Circuit (I2C)
        1. 5.12.2.1 I2C Electrical Data and Timing
          1. Table 5-66 I2C Timing Requirements
          2. Table 5-67 I2C Switching Characteristics
      3. 5.12.3 Power Management Bus (PMBus) Interface
        1. 5.12.3.1 PMBus Electrical Data and Timing
          1. Table 5-68 PMBus Electrical Characteristics
          2. Table 5-69 PMBus Fast Mode Switching Characteristics
          3. Table 5-70 PMBus Standard Mode Switching Characteristics
      4. 5.12.4 Serial Communications Interface (SCI)
      5. 5.12.5 Serial Peripheral Interface (SPI)
        1. 5.12.5.1 SPI Electrical Data and Timing
          1. 5.12.5.1.1 Non-High-Speed Master Mode Timings
            1. Table 5-71 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-72 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-73 SPI Master Mode Timing Requirements
          2. 5.12.5.1.2 Non-High-Speed Slave Mode Timings
            1. Table 5-74 SPI Slave Mode Switching Characteristics
            2. Table 5-75 SPI Slave Mode Timing Requirements
          3. 5.12.5.1.3 High-Speed Master Mode Timings
            1. Table 5-76 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-77 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-78 SPI High-Speed Master Mode Timing Requirements
          4. 5.12.5.1.4 High-Speed Slave Mode Timings
            1. Table 5-79 SPI High-Speed Slave Mode Switching Characteristics
            2. Table 5-80 SPI High-Speed Slave Mode Timing Requirements
      6. 5.12.6 Local Interconnect Network (LIN)
      7. 5.12.7 Fast Serial Interface (FSI)
        1. 5.12.7.1 FSI Transmitter
          1. 5.12.7.1.1 FSITX Electrical Data and Timing
            1. Table 5-81 FSITX Switching Characteristics
        2. 5.12.7.2 FSI Receiver
          1. 5.12.7.2.1 FSIRX Electrical Data and Timing
            1. Table 5-82 FSIRX Switching Characteristics
            2. Table 5-83 FSIRX Timing Requirements
        3. 5.12.7.3 FSI SPI Compatibility Mode
          1. 5.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. Table 5-84 FSITX SPI Signaling Mode Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 Control Law Accelerator (CLA) ROM Memory Map
      3. 6.3.3 Flash Memory Map
      4. 6.3.4 Peripheral Registers Memory Map
      5. 6.3.5 Memory Types
        1. 6.3.5.1 Dedicated RAM (Mx RAM)
        2. 6.3.5.2 Local Shared RAM (LSx RAM)
        3. 6.3.5.3 Global Shared RAM (GSx RAM)
        4. 6.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
      2. 6.6.2 Floating-Point Unit (FPU)
      3. 6.6.3 Trigonometric Math Unit (TMU)
      4. 6.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
    7. 6.7  Control Law Accelerator (CLA)
    8. 6.8  Direct Memory Access (DMA)
    9. 6.9  Boot ROM and Peripheral Booting
      1. 6.9.1 Configuring Alternate Boot Mode Select Pins
      2. 6.9.2 Configuring Alternate Boot Mode Options
      3. 6.9.3 GPIO Assignments
    10. 6.10 Dual Code Security Module
    11. 6.11 Watchdog
    12. 6.12 Configurable Logic Block (CLB)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Markings
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Support Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Analog Peripherals

The analog subsystem module is described in this section.

The analog modules on this device include the ADC, PGA, temperature sensor, buffered DAC, and CMPSS.

The analog subsystem has the following features:

  • Flexible voltage references
    • The ADCs are referenced to VREFHIx and VREFLOx pins.
      • VREFHIx pin voltage can be driven in externally or can be generated by an internal bandgap voltage reference.
      • The internal voltage reference range can be selected to be 0 V to 3.3 V or 0 V to 2.5 V.
  • The buffered DACs are referenced to VREFHIx and VREFLOx.
    • Alternately, these DACs can be referenced to the VDAC pin and VSSA.
  • The comparator DACs are referenced to VDDA and VSSA.
    • Alternately, these DACs can be referenced to the VDAC pin and VSSA.
  • Flexible pin usage
    • Buffered DAC outputs, comparator subsystem inputs, PGA functions, and digital inputs are multiplexed with ADC inputs
    • Internal connection to VREFLO on all ADCs for offset self-calibration

Figure 5-28 shows the Analog Subsystem Block Diagram for the 100-pin PZ LQFP.

Figure 5-29 shows the Analog Subsystem Block Diagram for the 64-pin PM LQFP.

Figure 5-30 shows the Analog Subsystem Block Diagram for the 56-pin RSH VQFN.

TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C AnalogSystem_100P_V0_prs945.gifFigure 5-28 Analog Subsystem Block Diagram (100-Pin PZ LQFP)
TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C AnalogSystem_64P_V1_prs945.gif
This PGA has no input/output connections on this package, but should be enabled and disabled at the same time as other PGAs with a shared PGA ground.
Figure 5-29 Analog Subsystem Block Diagram (64-Pin PM LQFP)
TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C AnalogSystem_56P_V1_prs945.gif
This PGA has no input/output connections on this package, but should be enabled and disabled at the same time as other PGAs with a shared PGA ground.
Figure 5-30 Analog Subsystem Block Diagram (56-Pin RSH VQFN)

Figure 5-31 shows the analog group connections. See Table 5-38 for the specific connections for each group for each package. Table 5-39 provides descriptions of the analog signals.

TMS320F280049 TMS320F280049C TMS320F280048 TMS320F280048C TMS320F280045 TMS320F280041 TMS320F280041C TMS320F280040 TMS320F280040C AnalogSystem_GroupConnections_V1_prs945.gif
On lower pin-count packages, the input to Gx_ADCC will share a pin with the PGA input. If the PGA input is unused, then the ADCC input can allow the pin to be used as an ADC input, a negative comparator input, or a digital input.
AIOs support digital input mode only.
The PGA RFILTER path is not available on some device revisions. See the TMS320F28004x MCUs Silicon Errata for more information.
Figure 5-31 Analog Group Connections

Table 5-38 Analog Pins and Internal Connections

PIN NAME GROUP NAME PACKAGE ALWAYS CONNECTED (NO MUX) COMPARATOR SUBSYSTEM (MUX) AIO INPUT
100 PZ 64 PM 56 RSH ADCA ADCB ADCC PGA DAC HIGH POSITIVE HIGH NEGATIVE LOW POSITIVE LOW NEGATIVE
VREFHIA - 25 16 14
VREFHIB - 24
VREFHIC -
VREFLOA - 27 17 15 A13
VREFLOB - 26 B13
VREFLOC - C13
Analog Group 1 CMP1
A3 G1_ADCAB 10 A3 HPMXSEL = 3 HNMXSEL = 0 LPMXSEL = 3 LNMXSEL = 0 AIO233
A2/B6/PGA1_OF PGA1_OF 9 9 8 A2 B6 PGA1_OF HPMXSEL = 0 LPMXSEL = 0 AIO224
C0 G1_ADCC 19 12 10 C0 HPMXSEL = 1 HNMXSEL = 1 LPMXSEL = 1 LNMXSEL = 1 AIO237
PGA1_IN PGA1_IN 18 PGA1_IN HPMXSEL = 2 LPMXSEL = 2
PGA1_GND PGA1_GND 14 10 9 PGA1_GND
- PGA1_OUT(1) A11 B7 PGA1_OUT HPMXSEL = 4 LPMXSEL = 4
Analog Group 2 CMP2
A5 G2_ADCAB 35 A5 HPMXSEL = 3 HNMXSEL = 0 LPMXSEL = 3 LNMXSEL = 0 AIO234
A4/B8/PGA2_OF PGA2_OF 36 23 21 A4 B8 PGA2_OF HPMXSEL = 0 LPMXSEL = 0 AIO225
C1 G2_ADCC 29 18 16 C1 HPMXSEL = 1 HNMXSEL = 1 LPMXSEL = 1 LNMXSEL = 1 AIO238
PGA2_IN PGA2_IN 30 PGA2_IN HPMXSEL = 2 LPMXSEL = 2
PGA2_GND PGA2_GND 32 20 18 PGA2_GND
- PGA2_OUT(1) A12 B9 PGA2_OUT HPMXSEL = 4 LPMXSEL = 4
Analog Group 3 CMP3
B3/VDAC G3_ADCAB 8 8 7 B3 VDAC HPMXSEL = 3 HNMXSEL = 0 LPMXSEL = 3 LNMXSEL = 0 AIO242
B2/C6/PGA3_OF PGA3_OF 7 7 6 B2 C6 PGA3_OF HPMXSEL = 0 LPMXSEL = 0 AIO226
C2 G3_ADCC 21 13 11 C2 HPMXSEL = 1 HNMXSEL = 1 LPMXSEL = 1 LNMXSEL = 1 AIO244
PGA3_IN PGA3_IN 20 PGA3_IN HPMXSEL = 2 LPMXSEL = 2
PGA3_GND PGA3_GND 15 10 9 PGA3_GND
- PGA3_OUT(1) B10 C7 PGA3_OUT HPMXSEL = 4 LPMXSEL = 4
Analog Group 4 CMP4
B5 G4_ADCAB B5 HPMXSEL = 3 HNMXSEL = 0 LPMXSEL = 3 LNMXSEL = 0 AIO243
B4/C8/PGA4_OF PGA4_OF 39 24 22 B4 C8 PGA4_OF HPMXSEL = 0 LPMXSEL = 0 AIO227
C3 G4_ADCC 31 19 17 C3 HPMXSEL = 1 HNMXSEL = 1 LPMXSEL = 1 LNMXSEL = 1 AIO245
PGA4_IN PGA4_IN PGA4_IN HPMXSEL = 2 LPMXSEL = 2
PGA4_GND PGA4_GND 32 20 18 PGA4_GND
- PGA4_OUT(1) B11 C9 PGA4_OUT HPMXSEL = 4 LPMXSEL = 4
Analog Group 5 CMP5
A7 G5_ADCAB A7 HPMXSEL = 3 HNMXSEL = 0 LPMXSEL = 3 LNMXSEL = 0 AIO235
A6/PGA5_OF PGA5_OF 6 6 A6 PGA5_OF HPMXSEL = 0 LPMXSEL = 0 AIO228
C4 G5_ADCC 17 11 C4 HPMXSEL = 1 HNMXSEL = 1 LPMXSEL = 1 LNMXSEL = 1 AIO239
PGA5_IN PGA5_IN 16 PGA5_IN HPMXSEL = 2 LPMXSEL = 2
PGA5_GND PGA5_GND 13 10 9 PGA5_GND
- PGA5_OUT(1) A14 PGA5_OUT HPMXSEL = 4 LPMXSEL = 4
Analog Group 6 CMP6
A9 G6_ADCAB 38 A9 HPMXSEL = 3 HNMXSEL = 0 LPMXSEL = 3 LNMXSEL = 0 AIO236
A8/PGA6_OF PGA6_OF 37 A8 PGA6_OF HPMXSEL = 0 LPMXSEL = 0 AIO229
C5 G6_ADCC 28 C5 HPMXSEL = 1 HNMXSEL = 1 LPMXSEL = 1 LNMXSEL = 1 AIO240
PGA6_IN PGA6_IN PGA6_IN HPMXSEL = 2 LPMXSEL = 2
PGA6_GND PGA6_GND 32 20 18 PGA6_GND
- PGA6_OUT(1) A15 PGA6_OUT HPMXSEL = 4 LPMXSEL = 4
Analog Group 7 CMP7
B0 G7_ADCAB 41 B0 HPMXSEL = 3 HNMXSEL = 0 LPMXSEL = 3 LNMXSEL = 0 AIO241
A10/B1/C10/PGA7_OF PGA7_OF(2) 40 25 23 A10 B1 C10 PGA7_OF HPMXSEL = 0 LPMXSEL = 0 AIO230
C14 G7_ADCC 44 C14 HPMXSEL = 1 HNMXSEL = 1 LPMXSEL = 1 LNMXSEL = 1 AIO246
PGA7_IN PGA7_IN 43 PGA7_IN HPMXSEL = 2 LPMXSEL = 2
PGA7_GND PGA7_GND 42 PGA7_GND
- PGA7_OUT(1) B12 C11 PGA7_OUT HPMXSEL = 4 LPMXSEL = 4
Other Analog
A0/B15/C15/DACA_OUT 23 15 13 A0 B15 C15 DACA_OUT AIO231
A1/DACB_OUT 22 14 12 A1 DACB_OUT AIO232
C12 C12 AIO247
- TempSensor(1) B14
Internal connection only; does not come to a device pin.
PGA functionality not available on 64-pin and 56-pin packages.

Table 5-39 Analog Signal Descriptions

SIGNAL NAME DESCRIPTION
AIOx Digital input on ADC pin
Ax ADC A Input
Bx ADC B Input
Cx ADC C Input
CMPx_DACH Comparator subsystem high DAC output
CMPx_DACL Comparator subsystem low DAC output
CMPx_HNy Comparator subsystem high comparator negative input
CMPx_HPy Comparator subsystem high comparator positive input
CMPx_LNy Comparator subsystem low comparator negative input
CMPx_LPy Comparator subsystem low comparator positive input
DACx_OUT Buffered DAC Output
PGAx_GND PGA Ground
PGAx_IN PGA Input
PGAx_OF PGA Output for filter
PGAx_OUT PGA Output to internal ADC
TempSensor Internal temperature sensor
VDAC Optional external reference voltage for on-chip DACs. There is a 100-pF capacitor to VSSA on this pin whether used for ADC input or DAC reference which cannot be disabled. If this pin is used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin.