SPRS945E January   2017  – April 2020 TMS320F280040 , TMS320F280040C , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280048 , TMS320F280048C , TMS320F280049 , TMS320F280049C

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 Analog Signals
      2. 4.3.2 Digital Signals
      3. 4.3.3 Power and Ground
      4. 4.3.4 Test, JTAG, and Reset
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 4.4.3 GPIO Input X-BAR
      4. 4.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 4.5 Pins With Internal Pullup and Pulldown
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 System Current Consumption (External Supply)
      2. Table 5-2 System Current Consumption (Internal VREG)
      3. Table 5-3 System Current Consumption (DCDC)
      4. 5.5.1     Operating Mode Test Description
      5. 5.5.2     Current Consumption Graphs
      6. 5.5.3     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PZ Package
      2. 5.7.2 PM Package
      3. 5.7.3 RSH Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  System
      1. 5.9.1 Power Management
        1. 5.9.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 5.9.1.2 Internal 1.2-V Switching Regulator (DC-DC)
          1. 5.9.1.2.1 PCB Layout and Component Guidelines
            1. Table 5-8 Recommended External Components
        3. 5.9.1.3 Deciding Between the LDO and the DC-DC
        4. 5.9.1.4 Power Sequencing
        5. 5.9.1.5 Power-On Reset (POR)
        6. 5.9.1.6 Brownout Reset (BOR)
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Sources
        2. 5.9.2.2 Reset Electrical Data and Timing
          1. Table 5-10 Reset (XRSn) Timing Requirements
          2. Table 5-11 Reset (XRSn) Switching Characteristics
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1 Clock Sources
        2. 5.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-13 Input Clock Frequency
            2. Table 5-14 XTAL Oscillator Characteristics
            3. Table 5-15 X1 Timing Requirements
            4. Table 5-16 PLL Lock Times
          2. 5.9.3.2.2 Internal Clock Frequencies
            1. Table 5-17 Internal Clock Frequencies
          3. 5.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-18 XCLKOUT Switching Characteristics
        3. 5.9.3.3 Input Clocks and PLLs
        4. 5.9.3.4 Crystal Oscillator
          1. Table 5-19 Crystal Oscillator Parameters
          2. Table 5-21 Crystal Oscillator Electrical Characteristics
        5. 5.9.3.5 Internal Oscillators
          1. Table 5-22 INTOSC Characteristics
      4. 5.9.4 Flash Parameters
      5. 5.9.5 Emulation/JTAG
        1. 5.9.5.1 JTAG Electrical Data and Timing
          1. Table 5-25 JTAG Timing Requirements
          2. Table 5-26 JTAG Switching Characteristics
        2. 5.9.5.2 cJTAG Electrical Data and Timing
          1. Table 5-27 cJTAG Timing Requirements
          2. Table 5-28 cJTAG Switching Characteristics
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO – Output Timing
          1. Table 5-29 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO – Input Timing
          1. Table 5-30 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
      7. 5.9.7 Interrupts
        1. 5.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-31 External Interrupt Timing Requirements
          2. Table 5-32 External Interrupt Switching Characteristics
      8. 5.9.8 Low-Power Modes
        1. 5.9.8.1 Clock-Gating Low-Power Modes
        2. 5.9.8.2 Low-Power Mode Wake-up Timing
          1. Table 5-34 IDLE Mode Timing Requirements
          2. Table 5-35 IDLE Mode Switching Characteristics
          3. Table 5-36 HALT Mode Timing Requirements
          4. Table 5-37 HALT Mode Switching Characteristics
    10. 5.10 Analog Peripherals
      1. 5.10.1 Analog-to-Digital Converter (ADC)
        1. 5.10.1.1 ADC Configurability
          1. 5.10.1.1.1 Signal Mode
        2. 5.10.1.2 ADC Electrical Data and Timing
          1. Table 5-41 ADC Operating Conditions
          2. Table 5-42 ADC Characteristics
          3. 5.10.1.2.1 ADC Input Model
          4. 5.10.1.2.2 ADC Timing Diagrams
      2. 5.10.2 Programmable Gain Amplifier (PGA)
        1. 5.10.2.1 PGA Electrical Data and Timing
          1. Table 5-47 PGA Operating Conditions
          2. Table 5-48 PGA Characteristics
          3. 5.10.2.1.1 PGA Typical Characteristics Graphs
      3. 5.10.3 Temperature Sensor
        1. 5.10.3.1 Temperature Sensor Electrical Data and Timing
          1. Table 5-49 Temperature Sensor Characteristics
      4. 5.10.4 Buffered Digital-to-Analog Converter (DAC)
        1. 5.10.4.1 Buffered DAC Electrical Data and Timing
          1. Table 5-50 Buffered DAC Operating Conditions
          2. Table 5-51 Buffered DAC Electrical Characteristics
          3. 5.10.4.1.1 Buffered DAC Illustrative Graphs
          4. 5.10.4.1.2 Buffered DAC Typical Characteristics Graphs
      5. 5.10.5 Comparator Subsystem (CMPSS)
        1. 5.10.5.1 CMPSS Electrical Data and Timing
          1. Table 5-52 Comparator Electrical Characteristics
          2. Table 5-53 CMPSS DAC Static Electrical Characteristics
          3. 5.10.5.1.1 CMPSS Illustrative Graphs
    11. 5.11 Control Peripherals
      1. 5.11.1 Enhanced Capture (eCAP)
        1. 5.11.1.1 eCAP Electrical Data and Timing
          1. Table 5-54 eCAP Timing Requirements
          2. Table 5-55 eCAP Switching Charcteristics
      2. 5.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
        1. 5.11.2.1 HRCAP Electrical Data and Timing
          1. Table 5-56 HRCAP Switching Characteristics
      3. 5.11.3 Enhanced Pulse Width Modulator (ePWM)
        1. 5.11.3.1 Control Peripherals Synchronization
        2. 5.11.3.2 ePWM Electrical Data and Timing
          1. Table 5-57 ePWM Timing Requirements
          2. Table 5-58 ePWM Switching Characteristics
          3. 5.11.3.2.1 Trip-Zone Input Timing
            1. Table 5-59 Trip-Zone Input Timing Requirements
        3. 5.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-60 External ADC Start-of-Conversion Switching Characteristics
      4. 5.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.11.4.1 HRPWM Electrical Data and Timing
          1. Table 5-61 High-Resolution PWM Characteristics
      5. 5.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.11.5.1 eQEP Electrical Data and Timing
          1. Table 5-62 eQEP Timing Requirements
          2. Table 5-63 eQEP Switching Characteristics
      6. 5.11.6 Sigma-Delta Filter Module (SDFM)
        1. 5.11.6.1 SDFM Electrical Data and Timing
          1. Table 5-64 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 5.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
          1. Table 5-65 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
    12. 5.12 Communications Peripherals
      1. 5.12.1 Controller Area Network (CAN)
      2. 5.12.2 Inter-Integrated Circuit (I2C)
        1. 5.12.2.1 I2C Electrical Data and Timing
          1. Table 5-66 I2C Timing Requirements
          2. Table 5-67 I2C Switching Characteristics
      3. 5.12.3 Power Management Bus (PMBus) Interface
        1. 5.12.3.1 PMBus Electrical Data and Timing
          1. Table 5-68 PMBus Electrical Characteristics
          2. Table 5-69 PMBus Fast Mode Switching Characteristics
          3. Table 5-70 PMBus Standard Mode Switching Characteristics
      4. 5.12.4 Serial Communications Interface (SCI)
      5. 5.12.5 Serial Peripheral Interface (SPI)
        1. 5.12.5.1 SPI Electrical Data and Timing
          1. 5.12.5.1.1 Non-High-Speed Master Mode Timings
            1. Table 5-71 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-72 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-73 SPI Master Mode Timing Requirements
          2. 5.12.5.1.2 Non-High-Speed Slave Mode Timings
            1. Table 5-74 SPI Slave Mode Switching Characteristics
            2. Table 5-75 SPI Slave Mode Timing Requirements
          3. 5.12.5.1.3 High-Speed Master Mode Timings
            1. Table 5-76 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-77 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-78 SPI High-Speed Master Mode Timing Requirements
          4. 5.12.5.1.4 High-Speed Slave Mode Timings
            1. Table 5-79 SPI High-Speed Slave Mode Switching Characteristics
            2. Table 5-80 SPI High-Speed Slave Mode Timing Requirements
      6. 5.12.6 Local Interconnect Network (LIN)
      7. 5.12.7 Fast Serial Interface (FSI)
        1. 5.12.7.1 FSI Transmitter
          1. 5.12.7.1.1 FSITX Electrical Data and Timing
            1. Table 5-81 FSITX Switching Characteristics
        2. 5.12.7.2 FSI Receiver
          1. 5.12.7.2.1 FSIRX Electrical Data and Timing
            1. Table 5-82 FSIRX Switching Characteristics
            2. Table 5-83 FSIRX Timing Requirements
        3. 5.12.7.3 FSI SPI Compatibility Mode
          1. 5.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. Table 5-84 FSITX SPI Signaling Mode Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 Control Law Accelerator (CLA) ROM Memory Map
      3. 6.3.3 Flash Memory Map
      4. 6.3.4 Peripheral Registers Memory Map
      5. 6.3.5 Memory Types
        1. 6.3.5.1 Dedicated RAM (Mx RAM)
        2. 6.3.5.2 Local Shared RAM (LSx RAM)
        3. 6.3.5.3 Global Shared RAM (GSx RAM)
        4. 6.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
      2. 6.6.2 Floating-Point Unit (FPU)
      3. 6.6.3 Trigonometric Math Unit (TMU)
      4. 6.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
    7. 6.7  Control Law Accelerator (CLA)
    8. 6.8  Direct Memory Access (DMA)
    9. 6.9  Boot ROM and Peripheral Booting
      1. 6.9.1 Configuring Alternate Boot Mode Select Pins
      2. 6.9.2 Configuring Alternate Boot Mode Options
      3. 6.9.3 GPIO Assignments
    10. 6.10 Dual Code Security Module
    11. 6.11 Watchdog
    12. 6.12 Configurable Logic Block (CLB)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Markings
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Support Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Analog Signals

Table 4-2 Analog Signals

SIGNAL NAME DESCRIPTION PIN TYPE GPIO 100 PZ 64 PMQ 64 PM 56 RSH
A0 ADC-A Input 0 I 23 15 15 13
A1 ADC-A Input 1 I 22 14 14 12
A2 ADC-A Input 2 I 9 9 9 8
A3 ADC-A Input 3 I 10
A4 ADC-A Input 4 I 36 23 23 21
A5 ADC-A Input 5 I 35
A6 ADC-A Input 6 I 6 6 6
A8 ADC-A Input 8 I 37
A9 ADC-A Input 9 I 38
A10 ADC-A Input 10 I 40 25 25 23
AIO224 Digital Input-224 on ADC Pin I 9 9 9 8
AIO225 Digital Input-225 on ADC Pin I 36 23 23 21
AIO226 Digital Input-226 on ADC Pin I 7 7 7 6
AIO227 Digital Input-227 on ADC Pin I 39 24 24 22
AIO228 Digital Input-228 on ADC Pin I 6 6 6
AIO229 Digital Input-229 on ADC Pin I 37
AIO230 Digital Input-230 on ADC Pin I 40 25 25 23
AIO231 Digital Input-231 on ADC Pin I 23 15 15 13
AIO232 Digital Input-232 on ADC Pin I 22 14 14 12
AIO233 Digital Input-233 on ADC Pin I 10
AIO234 Digital Input-234 on ADC Pin I 35
AIO236 Digital Input-236 on ADC Pin I 38
AIO237 Digital Input-237 on ADC Pin I 19 12 12 10
AIO238 Digital Input-238 on ADC Pin I 29 18 18 16
AIO239 Digital Input-239 on ADC Pin I 17 11 11
AIO240 Digital Input-240 on ADC Pin I 28
AIO241 Digital Input-241 on ADC Pin I 41
AIO242 Digital Input-242 on ADC Pin I 8 8 8 7
AIO244 Digital Input-244 on ADC Pin I 21 13 13 11
AIO245 Digital Input-245 on ADC Pin I 31 19 19 17
AIO246 Digital Input-246 on ADC Pin I 44
B0 ADC-B Input 0 I 41
B1 ADC-B Input 1 I 40 25 25 23
B2 ADC-B Input 2 I 7 7 7 6
B3 ADC-B Input 3 I 8 8 8 7
B4 ADC-B Input 4 I 39 24 24 22
B6 ADC-B Input 6 I 9 9 9 8
B8 ADC-B Input 8 I 36 23 23 21
B15 ADC-B Input 15 I 23 15 15 13
C0 ADC-C Input 0 I 19 12 12 10
C1 ADC-C Input 1 I 29 18 18 16
C2 ADC-C Input 2 I 21 13 13 11
C3 ADC-C Input 3 I 31 19 19 17
C4 ADC-C Input 4 I 17 11 11
C5 ADC-C Input 5 I 28
C6 ADC-C Input 6 I 7 7 7 6
C8 ADC-C Input 8 I 39 24 24 22
C10 ADC-C Input 10 I 40 25 25 23
C14 ADC-C Input 14 I 44
C15 ADC-C Input 15 I 23 15 15 13
CMP1_HN0 CMPSS-1 High Comparator Negative Input 0 I 10
CMP1_HN1 CMPSS-1 High Comparator Negative Input 1 I 19 12 12 10
CMP1_HP0 CMPSS-1 High Comparator Positive Input 0 I 9 9 9 8
CMP1_HP1 CMPSS-1 High Comparator Positive Input 1 I 19 12 12 10
CMP1_HP2 CMPSS-1 High Comparator Positive Input 2 I 18 12 12 10
CMP1_HP3 CMPSS-1 High Comparator Positive Input 3 I 10
CMP1_LN0 CMPSS-1 Low Comparator Negative Input 0 I 10
CMP1_LN1 CMPSS-1 Low Comparator Negative Input 1 I 19 12 12 10
CMP1_LP0 CMPSS-1 Low Comparator Positive Input 0 I 9 9 9 8
CMP1_LP1 CMPSS-1 Low Comparator Positive Input 1 I 19 12 12 10
CMP1_LP2 CMPSS-1 Low Comparator Positive Input 2 I 18 12 12 10
CMP1_LP3 CMPSS-1 Low Comparator Positive Input 3 I 10
CMP2_HN0 CMPSS-2 High Comparator Negative Input 0 I 35
CMP2_HN1 CMPSS-2 High Comparator Negative Input 1 I 29 18 18 16
CMP2_HP0 CMPSS-2 High Comparator Positive Input 0 I 36 23 23 21
CMP2_HP1 CMPSS-2 High Comparator Positive Input 1 I 29 18 18 16
CMP2_HP2 CMPSS-2 High Comparator Positive Input 2 I 30 18 18 16
CMP2_HP3 CMPSS-2 High Comparator Positive Input 3 I 35
CMP2_LN0 CMPSS-2 Low Comparator Negative Input 0 I 35
CMP2_LN1 CMPSS-2 Low Comparator Negative Input 1 I 29 18 18 16
CMP2_LP0 CMPSS-2 Low Comparator Positive Input 0 I 36 23 23 21
CMP2_LP1 CMPSS-2 Low Comparator Positive Input 1 I 29 18 18 16
CMP2_LP2 CMPSS-2 Low Comparator Positive Input 2 I 30 18 18 16
CMP2_LP3 CMPSS-2 Low Comparator Positive Input 3 I 35
CMP3_HN0 CMPSS-3 High Comparator Negative Input 0 I 8 8 8 7
CMP3_HN1 CMPSS-3 High Comparator Negative Input 1 I 21 13 13 11
CMP3_HP0 CMPSS-3 High Comparator Positive Input 0 I 7 7 7 6
CMP3_HP1 CMPSS-3 High Comparator Positive Input 1 I 21 13 13 11
CMP3_HP2 CMPSS-3 High Comparator Positive Input 2 I 20 13 13 11
CMP3_HP3 CMPSS-3 High Comparator Positive Input 3 I 8 8 8 7
CMP3_LN0 CMPSS-3 Low Comparator Negative Input 0 I 8 8 8 7
CMP3_LN1 CMPSS-3 Low Comparator Negative Input 1 I 21 13 13 11
CMP3_LP0 CMPSS-3 Low Comparator Positive Input 0 I 7 7 7 6
CMP3_LP1 CMPSS-3 Low Comparator Positive Input 1 I 21 13 13 11
CMP3_LP2 CMPSS-3 Low Comparator Positive Input 2 I 20 13 13 11
CMP3_LP3 CMPSS-3 Low Comparator Positive Input 3 I 8 8 8 7
CMP4_HN1 CMPSS-4 High Comparator Negative Input 1 I 31 19 19 17
CMP4_HP0 CMPSS-4 High Comparator Positive Input 0 I 39 24 24 22
CMP4_HP1 CMPSS-4 High Comparator Positive Input 1 I 31 19 19 17
CMP4_HP2 CMPSS-4 High Comparator Positive Input 2 I 31 19 19 17
CMP4_LN1 CMPSS-4 Low Comparator Negative Input 1 I 31 19 19 17
CMP4_LP0 CMPSS-4 Low Comparator Positive Input 0 I 39 24 24 22
CMP4_LP1 CMPSS-4 Low Comparator Positive Input 1 I 31 19 19 17
CMP4_LP2 CMPSS-4 Low Comparator Positive Input 2 I 31 19 19 17
CMP5_HN1 CMPSS-5 High Comparator Negative Input 1 I 17 11 11
CMP5_HP0 CMPSS-5 High Comparator Positive Input 0 I 6 6 6
CMP5_HP1 CMPSS-5 High Comparator Positive Input 1 I 17 11 11
CMP5_HP2 CMPSS-5 High Comparator Positive Input 2 I 16 11 11
CMP5_LN1 CMPSS-5 Low Comparator Negative Input 1 I 17 11 11
CMP5_LP0 CMPSS-5 Low Comparator Positive Input 0 I 6 6 6
CMP5_LP1 CMPSS-5 Low Comparator Positive Input 1 I 17 11 11
CMP5_LP2 CMPSS-5 Low Comparator Positive Input 2 I 16 11 11
CMP6_HN0 CMPSS-6 High Comparator Negative Input 0 I 38
CMP6_HN1 CMPSS-6 High Comparator Negative Input 1 I 28
CMP6_HP0 CMPSS-6 High Comparator Positive Input 0 I 37
CMP6_HP1 CMPSS-6 High Comparator Positive Input 1 I 28
CMP6_HP2 CMPSS-6 High Comparator Positive Input 2 I 28
CMP6_HP3 CMPSS-6 High Comparator Positive Input 3 I 38
CMP6_LN0 CMPSS-6 Low Comparator Negative Input 0 I 38
CMP6_LN1 CMPSS-6 Low Comparator Negative Input 1 I 28
CMP6_LP0 CMPSS-6 Low Comparator Positive Input 0 I 37
CMP6_LP1 CMPSS-6 Low Comparator Positive Input 1 I 28
CMP6_LP2 CMPSS-6 Low Comparator Positive Input 2 I 28
CMP6_LP3 CMPSS-6 Low Comparator Positive Input 3 I 38
CMP7_HN0 CMPSS-7 High Comparator Negative Input 0 I 41
CMP7_HN1 CMPSS-7 High Comparator Negative Input 1 I 44
CMP7_HP0 CMPSS-7 High Comparator Positive Input 0 I 40 25 25 23
CMP7_HP1 CMPSS-7 High Comparator Positive Input 1 I 44
CMP7_HP2 CMPSS-7 High Comparator Positive Input 2 I 43
CMP7_HP3 CMPSS-7 High Comparator Positive Input 3 I 41
CMP7_LN0 CMPSS-7 Low Comparator Negative Input 0 I 41
CMP7_LN1 CMPSS-7 Low Comparator Negative Input 1 I 44
CMP7_LP0 CMPSS-7 Low Comparator Positive Input 0 I 40 25 25 23
CMP7_LP1 CMPSS-7 Low Comparator Positive Input 1 I 44
CMP7_LP2 CMPSS-7 Low Comparator Positive Input 2 I 43
CMP7_LP3 CMPSS-7 Low Comparator Positive Input 3 I 41
DACA_OUT Buffered DAC-A Output O 23 15 15 13
DACB_OUT Buffered DAC-B Output O 22 14 14 12
PGA1_GND PGA-1 Ground I 14 10 10 9
PGA1_IN PGA-1 Input I 18 12 12 10
PGA1_OF PGA-1 Output Filter (Optional) O 9 9 9 8
PGA2_GND PGA-2 Ground I 32 20 20 18
PGA2_IN PGA-2 Input I 30 18 18 16
PGA2_OF PGA-2 Output Filter (Optional) O 36 23 23 21
PGA3_GND PGA-3 Ground I 15 10 10 9
PGA3_IN PGA-3 Input I 20 13 13 11
PGA3_OF PGA-3 Output Filter (Optional) O 7 7 7 6
PGA4_GND PGA-4 Ground I 32 20 20 18
PGA4_IN PGA-4 Input I 31 19 19 17
PGA4_OF PGA-4 Output Filter (Optional) O 39 24 24 22
PGA5_GND PGA-5 Ground I 13 10 10 9
PGA5_IN PGA-5 Input I 16 11 11
PGA5_OF PGA-5 Output Filter (Optional) O 6 6 6
PGA6_GND PGA-6 Ground I 32 20 20 18
PGA6_IN PGA-6 Input I 28
PGA6_OF PGA-6 Output Filter (Optional) O 37
PGA7_GND PGA-7 Ground I 42
PGA7_IN PGA-7 Input I 43
PGA7_OF PGA-7 Output Filter (Optional) O 40 25 25 23
VDAC Optional external reference voltage for on-chip DACs. There is a 100-pF capacitor to VSSA on this pin whether used for ADC input or DAC reference which cannot be disabled. If this pin is being used as a reference for the on-chip DACs, place at least a 1-µF capacitor on this pin. I 8 8 8 7
VREFHIA ADC-A High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHIA and VREFLOA pins. Do not load this pin externally in either internal or external reference mode. I/O 25 16 16 14
VREFHIB ADC-B High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHIB and VREFLOB pins. Do not load this pin externally in either internal or external reference mode. I/O 24 16 16 14
VREFHIC ADC-C High Reference. In external reference mode, externally drive the high reference voltage onto this pin. In internal reference mode, a voltage is driven onto this pin by the device. In either mode, place at least a 2.2-µF capacitor on this pin. This capacitor should be placed as close to the device as possible between the VREFHIC and VREFLOC pins. Do not load this pin externally in either internal or external reference mode. I/O 24 16 16 14
VREFLOA ADC-A Low Reference I 27 17 17 15
VREFLOB ADC-B Low Reference I 26 17 17 15
VREFLOC ADC-C Low Reference I 26 17 17 15