IDLE and HALT modes on this device are similar to those on other C28x devices. Table 5-33 describes the effect on the system when any of the clock-gating low-power modes are entered.
|Clock to modules connected to PERx.SYSCLK||Active||Gated|
|WDCLK||Active||Gated if CLKSRCCTL1.WDHALTI = 0|
|PLL||Powered||Software must power down PLL before entering HALT.|
|INTOSC1||Powered||Powered down if CLKSRCCTL1.WDHALTI = 0|
|INTOSC2||Powered||Powered down if CLKSRCCTL1.WDHALTI = 0|