For applications that do not need to use all functions of the device, Table 4-10 lists acceptable conditioning for any unused pins. When multiple options are listed in Table 4-10, any option is acceptable. Pins not listed in Table 4-10 must be connected according to Section 4.
|SIGNAL NAME||ACCEPTABLE PRACTICE|
|Analog input pins with DACx_OUT||
|Analog input pins with PGAx_OUTF||
|Analog input pins (except for DACx_OUT and PGAx_OUTF)||
|PGAx_GND||Tie to VSSA|
|VREFHIx||Tie to VDDA (applies only if ADC or DAC are not used in the application)|
|VREFLOx||Tie to VSSA|
|FLT1 (Flash Test pin 1)||
|FLT2 (Flash Test pin 2)||
|GPIO35/TDI||When TDI mux option is selected (default), the GPIO is in Input mode.
|GPIO37/TDO||When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity; otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
|VREGENZ||Tie to VDDIO if internal regulator is not used|
|X1||Tie to VSS|
|POWER AND GROUND|
|VDD||All VDD pins must be connected per Section 4.3.|
|VDDA||If a dedicated analog supply is not used, tie to VDDIO.|
|VDDIO||All VDDIO pins must be connected per Section 4.3.|
|VDDIO_SW||Always tie to VDDIO.|
|VSS||All VSS pins must be connected to board ground.|
|VSS_SW||Always tie to VSS.|
|VSSA||If an analog ground is not used, tie to VSS.|