6.7 Control Law Accelerator (CLA)
The CLA Type-2 is an independent, fully programmable, 32-bit floating-point math processor that brings concurrent control-loop execution to the C28x family. The low interrupt-latency of the CLA allows it to read ADC samples "just-in-time." This significantly reduces the ADC sample to output delay to enable faster system response and higher MHz control loops. By using the CLA to service time-critical control loops, the main CPU is free to perform other system tasks such as communications and diagnostics.
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system response and higher frequency control loops. Using the CLA for time-critical tasks frees up the main CPU to perform other system and communication functions concurrently.
The following is a list of major features of the CLA:
- Clocked at the same rate as the main CPU (SYSCLKOUT).
- An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
- Complete bus architecture:
- Program Address Bus (PAB) and Program Data Bus (PDB)
- Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and Data Write Data Bus (DWDB)
- Independent 8-stage pipeline.
- 16-bit program counter (MPC)
- Four 32-bit result registers (MR0 to MR3)
- Two 16-bit auxiliary registers (MAR0, MAR1)
- Status register (MSTF)
- Instruction set includes:
- IEEE single-precision (32-bit) floating-point math operations
- Floating-point math with parallel load or store
- Floating-point multiply with parallel add or subtract
- 1/X and 1/sqrt(X) estimations
- Data type conversions
- Conditional branch and call
- Data load/store operations
- The CLA program code can consist of up to eight tasks or interrupt service routines, or seven tasks and a main background task.
- The start address of each task is specified by the MVECT registers.
- No limit on task size as long as the tasks fit within the configurable CLA program memory space.
- One task is serviced at a time until its completion. There is no nesting of tasks.
- Upon task completion a task-specific interrupt is flagged within the PIE.
- When a task finishes the next highest-priority pending task is automatically started.
- The Type-2 CLA can have a main task that runs continuously in the background, while other high-priority events trigger a foreground task.
- Task trigger mechanisms:
- C28x CPU through the IACK instruction
- Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus on which the CLA assumes secondary ownership.
- Task8 can be set to be the background task, while Tasks 1 to 7 take peripheral triggers.
- Memory and Shared Peripherals:
- Two dedicated message RAMs for communication between the CLA and the main CPU.
- The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
Figure 6-2 shows the CLA block diagram.
Figure 6-2 CLA Block Diagram