SPRS945E January   2017  – April 2020 TMS320F280040 , TMS320F280040C , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280048 , TMS320F280048C , TMS320F280049 , TMS320F280049C

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 Analog Signals
      2. 4.3.2 Digital Signals
      3. 4.3.3 Power and Ground
      4. 4.3.4 Test, JTAG, and Reset
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 4.4.3 GPIO Input X-BAR
      4. 4.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 4.5 Pins With Internal Pullup and Pulldown
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 System Current Consumption (External Supply)
      2. Table 5-2 System Current Consumption (Internal VREG)
      3. Table 5-3 System Current Consumption (DCDC)
      4. 5.5.1     Operating Mode Test Description
      5. 5.5.2     Current Consumption Graphs
      6. 5.5.3     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PZ Package
      2. 5.7.2 PM Package
      3. 5.7.3 RSH Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  System
      1. 5.9.1 Power Management
        1. 5.9.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 5.9.1.2 Internal 1.2-V Switching Regulator (DC-DC)
          1. 5.9.1.2.1 PCB Layout and Component Guidelines
            1. Table 5-8 Recommended External Components
        3. 5.9.1.3 Deciding Between the LDO and the DC-DC
        4. 5.9.1.4 Power Sequencing
        5. 5.9.1.5 Power-On Reset (POR)
        6. 5.9.1.6 Brownout Reset (BOR)
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Sources
        2. 5.9.2.2 Reset Electrical Data and Timing
          1. Table 5-10 Reset (XRSn) Timing Requirements
          2. Table 5-11 Reset (XRSn) Switching Characteristics
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1 Clock Sources
        2. 5.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-13 Input Clock Frequency
            2. Table 5-14 XTAL Oscillator Characteristics
            3. Table 5-15 X1 Timing Requirements
            4. Table 5-16 PLL Lock Times
          2. 5.9.3.2.2 Internal Clock Frequencies
            1. Table 5-17 Internal Clock Frequencies
          3. 5.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-18 XCLKOUT Switching Characteristics
        3. 5.9.3.3 Input Clocks and PLLs
        4. 5.9.3.4 Crystal Oscillator
          1. Table 5-19 Crystal Oscillator Parameters
          2. Table 5-21 Crystal Oscillator Electrical Characteristics
        5. 5.9.3.5 Internal Oscillators
          1. Table 5-22 INTOSC Characteristics
      4. 5.9.4 Flash Parameters
      5. 5.9.5 Emulation/JTAG
        1. 5.9.5.1 JTAG Electrical Data and Timing
          1. Table 5-25 JTAG Timing Requirements
          2. Table 5-26 JTAG Switching Characteristics
        2. 5.9.5.2 cJTAG Electrical Data and Timing
          1. Table 5-27 cJTAG Timing Requirements
          2. Table 5-28 cJTAG Switching Characteristics
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO – Output Timing
          1. Table 5-29 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO – Input Timing
          1. Table 5-30 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
      7. 5.9.7 Interrupts
        1. 5.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-31 External Interrupt Timing Requirements
          2. Table 5-32 External Interrupt Switching Characteristics
      8. 5.9.8 Low-Power Modes
        1. 5.9.8.1 Clock-Gating Low-Power Modes
        2. 5.9.8.2 Low-Power Mode Wake-up Timing
          1. Table 5-34 IDLE Mode Timing Requirements
          2. Table 5-35 IDLE Mode Switching Characteristics
          3. Table 5-36 HALT Mode Timing Requirements
          4. Table 5-37 HALT Mode Switching Characteristics
    10. 5.10 Analog Peripherals
      1. 5.10.1 Analog-to-Digital Converter (ADC)
        1. 5.10.1.1 ADC Configurability
          1. 5.10.1.1.1 Signal Mode
        2. 5.10.1.2 ADC Electrical Data and Timing
          1. Table 5-41 ADC Operating Conditions
          2. Table 5-42 ADC Characteristics
          3. 5.10.1.2.1 ADC Input Model
          4. 5.10.1.2.2 ADC Timing Diagrams
      2. 5.10.2 Programmable Gain Amplifier (PGA)
        1. 5.10.2.1 PGA Electrical Data and Timing
          1. Table 5-47 PGA Operating Conditions
          2. Table 5-48 PGA Characteristics
          3. 5.10.2.1.1 PGA Typical Characteristics Graphs
      3. 5.10.3 Temperature Sensor
        1. 5.10.3.1 Temperature Sensor Electrical Data and Timing
          1. Table 5-49 Temperature Sensor Characteristics
      4. 5.10.4 Buffered Digital-to-Analog Converter (DAC)
        1. 5.10.4.1 Buffered DAC Electrical Data and Timing
          1. Table 5-50 Buffered DAC Operating Conditions
          2. Table 5-51 Buffered DAC Electrical Characteristics
          3. 5.10.4.1.1 Buffered DAC Illustrative Graphs
          4. 5.10.4.1.2 Buffered DAC Typical Characteristics Graphs
      5. 5.10.5 Comparator Subsystem (CMPSS)
        1. 5.10.5.1 CMPSS Electrical Data and Timing
          1. Table 5-52 Comparator Electrical Characteristics
          2. Table 5-53 CMPSS DAC Static Electrical Characteristics
          3. 5.10.5.1.1 CMPSS Illustrative Graphs
    11. 5.11 Control Peripherals
      1. 5.11.1 Enhanced Capture (eCAP)
        1. 5.11.1.1 eCAP Electrical Data and Timing
          1. Table 5-54 eCAP Timing Requirements
          2. Table 5-55 eCAP Switching Charcteristics
      2. 5.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
        1. 5.11.2.1 HRCAP Electrical Data and Timing
          1. Table 5-56 HRCAP Switching Characteristics
      3. 5.11.3 Enhanced Pulse Width Modulator (ePWM)
        1. 5.11.3.1 Control Peripherals Synchronization
        2. 5.11.3.2 ePWM Electrical Data and Timing
          1. Table 5-57 ePWM Timing Requirements
          2. Table 5-58 ePWM Switching Characteristics
          3. 5.11.3.2.1 Trip-Zone Input Timing
            1. Table 5-59 Trip-Zone Input Timing Requirements
        3. 5.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-60 External ADC Start-of-Conversion Switching Characteristics
      4. 5.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.11.4.1 HRPWM Electrical Data and Timing
          1. Table 5-61 High-Resolution PWM Characteristics
      5. 5.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.11.5.1 eQEP Electrical Data and Timing
          1. Table 5-62 eQEP Timing Requirements
          2. Table 5-63 eQEP Switching Characteristics
      6. 5.11.6 Sigma-Delta Filter Module (SDFM)
        1. 5.11.6.1 SDFM Electrical Data and Timing
          1. Table 5-64 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 5.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
          1. Table 5-65 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
    12. 5.12 Communications Peripherals
      1. 5.12.1 Controller Area Network (CAN)
      2. 5.12.2 Inter-Integrated Circuit (I2C)
        1. 5.12.2.1 I2C Electrical Data and Timing
          1. Table 5-66 I2C Timing Requirements
          2. Table 5-67 I2C Switching Characteristics
      3. 5.12.3 Power Management Bus (PMBus) Interface
        1. 5.12.3.1 PMBus Electrical Data and Timing
          1. Table 5-68 PMBus Electrical Characteristics
          2. Table 5-69 PMBus Fast Mode Switching Characteristics
          3. Table 5-70 PMBus Standard Mode Switching Characteristics
      4. 5.12.4 Serial Communications Interface (SCI)
      5. 5.12.5 Serial Peripheral Interface (SPI)
        1. 5.12.5.1 SPI Electrical Data and Timing
          1. 5.12.5.1.1 Non-High-Speed Master Mode Timings
            1. Table 5-71 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-72 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-73 SPI Master Mode Timing Requirements
          2. 5.12.5.1.2 Non-High-Speed Slave Mode Timings
            1. Table 5-74 SPI Slave Mode Switching Characteristics
            2. Table 5-75 SPI Slave Mode Timing Requirements
          3. 5.12.5.1.3 High-Speed Master Mode Timings
            1. Table 5-76 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-77 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-78 SPI High-Speed Master Mode Timing Requirements
          4. 5.12.5.1.4 High-Speed Slave Mode Timings
            1. Table 5-79 SPI High-Speed Slave Mode Switching Characteristics
            2. Table 5-80 SPI High-Speed Slave Mode Timing Requirements
      6. 5.12.6 Local Interconnect Network (LIN)
      7. 5.12.7 Fast Serial Interface (FSI)
        1. 5.12.7.1 FSI Transmitter
          1. 5.12.7.1.1 FSITX Electrical Data and Timing
            1. Table 5-81 FSITX Switching Characteristics
        2. 5.12.7.2 FSI Receiver
          1. 5.12.7.2.1 FSIRX Electrical Data and Timing
            1. Table 5-82 FSIRX Switching Characteristics
            2. Table 5-83 FSIRX Timing Requirements
        3. 5.12.7.3 FSI SPI Compatibility Mode
          1. 5.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. Table 5-84 FSITX SPI Signaling Mode Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 Control Law Accelerator (CLA) ROM Memory Map
      3. 6.3.3 Flash Memory Map
      4. 6.3.4 Peripheral Registers Memory Map
      5. 6.3.5 Memory Types
        1. 6.3.5.1 Dedicated RAM (Mx RAM)
        2. 6.3.5.2 Local Shared RAM (LSx RAM)
        3. 6.3.5.3 Global Shared RAM (GSx RAM)
        4. 6.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
      2. 6.6.2 Floating-Point Unit (FPU)
      3. 6.6.3 Trigonometric Math Unit (TMU)
      4. 6.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
    7. 6.7  Control Law Accelerator (CLA)
    8. 6.8  Direct Memory Access (DMA)
    9. 6.9  Boot ROM and Peripheral Booting
      1. 6.9.1 Configuring Alternate Boot Mode Select Pins
      2. 6.9.2 Configuring Alternate Boot Mode Options
      3. 6.9.3 GPIO Assignments
    10. 6.10 Dual Code Security Module
    11. 6.11 Watchdog
    12. 6.12 Configurable Logic Block (CLB)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Markings
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Support Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Digital Signals

Table 4-3 Digital Signals

SIGNAL NAME DESCRIPTION PIN TYPE GPIO 100 PZ 64 PMQ 64 PM 56 RSH
ADCSOCAO ADC Start of Conversion A Output for External ADC (from ePWM modules) O 8 74 47 47 42
ADCSOCBO ADC Start of Conversion B Output for External ADC (from ePWM modules) O 10 93 63 63
CANA_RX CAN-A Receive I 18, 30, 33, 35, 5 53, 63, 68, 89, 98 32, 39, 41, 61 32, 39, 41, 61 29, 36, 38, 55
CANA_TX CAN-A Transmit O 31, 32, 37, 4 61, 64, 75, 99 37, 40, 48 37, 40, 48 34, 37, 43
CANB_RX CAN-B Receive I 10, 13, 17, 39, 59, 7 50, 55, 84, 91, 92, 93 34, 57, 63 29, 34, 57, 63 26, 31, 52
CANB_TX CAN-B Transmit O 12, 16, 58, 6, 8 51, 54, 67, 74, 97 33, 47, 64 30, 33, 47, 64 1, 27, 30, 42
EPWM1_A ePWM-1 Output A O 0 79 52 52 47
EPWM1_B ePWM-1 Output B O 1 78 51 51 46
EPWM2_A ePWM-2 Output A O 2 77 50 50 45
EPWM2_B ePWM-2 Output B O 3 76 49 49 44
EPWM3_A ePWM-3 Output A O 4 75 48 48 43
EPWM3_B ePWM-3 Output B O 5 89 61 61 55
EPWM4_A ePWM-4 Output A O 6 97 64 64 1
EPWM4_B ePWM-4 Output B O 7 84 57 57 52
EPWM5_A ePWM-5 Output A O 16, 8 54, 74 33, 47 33, 47 30, 42
EPWM5_B ePWM-5 Output B O 17, 9 55, 90 34, 62 34, 62 31, 56
EPWM6_A ePWM-6 Output A O 10, 18 68, 93 41, 63 41, 63 38
EPWM6_B ePWM-6 Output B O 11 52 31 31 28
EPWM7_A ePWM-7 Output A O 12, 28 1, 51 2 2, 30 27, 3
EPWM7_B ePWM-7 Output B O 13, 29 100, 50 1 1, 29 2, 26
EPWM8_A ePWM-8 Output A O 14, 24 56, 96 35 35 32
EPWM8_B ePWM-8 Output B O 15, 32 64, 95 40 40 37
EQEP1_A eQEP-1 Input A I 10, 28, 35, 40, 56, 6 1, 63, 65, 85, 93, 97 2, 39, 63, 64 2, 39, 63, 64 1, 3, 36
EQEP1_B eQEP-1 Input B I 11, 29, 37, 57, 7 100, 52, 61, 66, 84 1, 31, 37, 57 1, 31, 37, 57 2, 28, 34, 52
EQEP1_INDEX eQEP-1 Index I/O 13, 17, 31, 59, 9 50, 55, 90, 92, 99 34, 62 29, 34, 62 26, 31, 56
EQEP1_STROBE eQEP-1 Strobe I/O 12, 16, 22, 30, 58, 8 51, 54, 67, 74, 83, 98 33, 47, 56 30, 33, 47, 56 27, 30, 42, 51
EQEP2_A eQEP-2 Input A I 14, 18, 24 56, 68, 96 35, 41 35, 41 32, 38
EQEP2_B eQEP-2 Input B I 15, 25 57, 95
EQEP2_INDEX eQEP-2 Index I/O 26, 29, 57 100, 58, 66 1 1 2
EQEP2_STROBE eQEP-2 Strobe I/O 27, 28, 56 1, 59, 65 2 2 3
ERRORSTS Error Status Output. This signal requires an external pullup. O 24, 28, 29 1, 100, 56 1, 2, 35 1, 2, 35 2, 3, 32
FSIRXA_CLK FSIRX-A Input Clock I 13, 33, 39, 4 50, 53, 75, 91 32, 48 29, 32, 48 26, 29, 43
FSIRXA_D0 FSIRX-A Primary Data Input I 12, 3, 32, 40 51, 64, 76, 85 40, 49 30, 40, 49 27, 37, 44
FSIRXA_D1 FSIRX-A Optional Additional Data Input I 11, 2, 31 52, 77, 99 31, 50 31, 50 28, 45
FSITXA_CLK FSITX-A Output Clock O 10, 27, 7 59, 84, 93 57, 63 57, 63 52
FSITXA_D0 FSITX-A Primary Data Output O 26, 6, 9 58, 90, 97 62, 64 62, 64 1, 56
FSITXA_D1 FSITX-A Optional Additional Data Output O 25, 5, 8 57, 74, 89 47, 61 47, 61 42, 55
GPIO0 General-Purpose Input Output 0 I/O 0 79 52 52 47
GPIO1 General-Purpose Input Output 1 I/O 1 78 51 51 46
GPIO2 General-Purpose Input Output 2 I/O 2 77 50 50 45
GPIO3 General-Purpose Input Output 3 I/O 3 76 49 49 44
GPIO4 General-Purpose Input Output 4 I/O 4 75 48 48 43
GPIO5 General-Purpose Input Output 5 I/O 5 89 61 61 55
GPIO6 General-Purpose Input Output 6 I/O 6 97 64 64 1
GPIO7 General-Purpose Input Output 7 I/O 7 84 57 57 52
GPIO8 General-Purpose Input Output 8 I/O 8 74 47 47 42
GPIO9 General-Purpose Input Output 9 I/O 9 90 62 62 56
GPIO10 General-Purpose Input Output 10 I/O 10 93 63 63
GPIO11 General-Purpose Input Output 11 I/O 11 52 31 31 28
GPIO12 General-Purpose Input Output 12 I/O 12 51 30 27
GPIO13 General-Purpose Input Output 13 I/O 13 50 29 26
GPIO14 General-Purpose Input Output 14 I/O 14 96
GPIO15 General-Purpose Input Output 15 I/O 15 95
GPIO16 General-Purpose Input Output 16 I/O 16 54 33 33 30
GPIO17 General-Purpose Input Output 17 I/O 17 55 34 34 31
GPIO18_X2 General-Purpose Input Output 18. This pin and its digital mux options can only be used when the system is clocked by INTOSC and X1 has an external pulldown resistor (recommended 1 kΩ). I/O 18 68 41 41 38
GPIO20 General-Purpose Input Output 20 I/O 20
GPIO21 General-Purpose Input Output 21 I/O 21
GPIO22_VFBSW General-Purpose Input Output 22. This pin is configured for DC-DC mode by default. If the internal DC-DC regulator is not used, this can be configured as General-Purpose Input Output 22 by disabling DC-DC and clearing their bits in GPAAMSEL register. I/O 22 83 56 56 51
GPIO23_VSW General-Purpose Input Output 23. This pin is configured for DC-DC mode by default. If the internal DC-DC regulator is not used, this can be configured as General-Purpose Input Output 23 by disabling DC-DC and clearing their bits in GPAAMSEL register. This pin has an internal capacitance of approximately 100 pF. TI Recommends using an alternate GPIO, or using this pin only for applications which do not require a fast switching response. I/O 23 81 54 54 49
GPIO24 General-Purpose Input Output 24 I/O 24 56 35 35 32
GPIO25 General-Purpose Input Output 25 I/O 25 57
GPIO26 General-Purpose Input Output 26 I/O 26 58
GPIO27 General-Purpose Input Output 27 I/O 27 59
GPIO28 General-Purpose Input Output 28 I/O 28 1 2 2 3
GPIO29 General-Purpose Input Output 29 I/O 29 100 1 1 2
GPIO30 General-Purpose Input Output 30 I/O 30 98
GPIO31 General-Purpose Input Output 31 I/O 31 99
GPIO32 General-Purpose Input Output 32 I/O 32 64 40 40 37
GPIO33 General-Purpose Input Output 33 I/O 33 53 32 32 29
GPIO34 General-Purpose Input Output 34 I/O 34 94
GPIO35 General-Purpose Input Output 35 I/O 35 63 39 39 36
GPIO37 General-Purpose Input Output 37 I/O 37 61 37 37 34
GPIO39 General-Purpose Input Output 39 I/O 39 91
GPIO40 General-Purpose Input Output 40 I/O 40 85
GPIO41 General-Purpose Input Output 41 I/O 41
GPIO42 General-Purpose Input Output 42 I/O 42
GPIO43 General-Purpose Input Output 43 I/O 43
GPIO44 General-Purpose Input Output 44 I/O 44
GPIO45 General-Purpose Input Output 45 I/O 45
GPIO46 General-Purpose Input Output 46 I/O 46
GPIO47 General-Purpose Input Output 47 I/O 47
GPIO48 General-Purpose Input Output 48 I/O 48
GPIO49 General-Purpose Input Output 49 I/O 49
GPIO50 General-Purpose Input Output 50 I/O 50
GPIO51 General-Purpose Input Output 51 I/O 51
GPIO52 General-Purpose Input Output 52 I/O 52
GPIO53 General-Purpose Input Output 53 I/O 53
GPIO54 General-Purpose Input Output 54 I/O 54
GPIO55 General-Purpose Input Output 55 I/O 55
GPIO56 General-Purpose Input Output 56 I/O 56 65
GPIO57 General-Purpose Input Output 57 I/O 57 66
GPIO58 General-Purpose Input Output 58 I/O 58 67
GPIO59 General-Purpose Input Output 59 I/O 59 92
I2CA_SCL I2C-A Open-Drain Bidirectional Clock I/OD 1, 18, 27, 33, 37, 8 53, 59, 61, 68, 74, 78 32, 37, 41, 47, 51 32, 37, 41, 47, 51 29, 34, 38, 42, 46
I2CA_SDA I2C-A Open-Drain Bidirectional Data I/OD 0, 10, 26, 32, 35 58, 63, 64, 79, 93 39, 40, 52, 63 39, 40, 52, 63 36, 37, 47
LINA_RX LIN-A Receive I 29, 33, 35, 59 100, 53, 63, 92 1, 32, 39 1, 32, 39 2, 29, 36
LINA_TX LIN-A Transmit O 22, 28, 32, 37, 58 1, 61, 64, 67, 83 2, 37, 40, 56 2, 37, 40, 56 3, 34, 37, 51
OUTPUTXBAR1 Output X-BAR Output 1 O 2, 24, 34, 58 56, 67, 77, 94 35, 50 35, 50 32, 45
OUTPUTXBAR2 Output X-BAR Output 2 O 25, 3, 37, 59 57, 61, 76, 92 37, 49 37, 49 34, 44
OUTPUTXBAR3 Output X-BAR Output 3 O 14, 26, 4, 5 58, 75, 89, 96 48, 61 48, 61 43, 55
OUTPUTXBAR4 Output X-BAR Output 4 O 15, 27, 33, 6 53, 59, 95, 97 32, 64 32, 64 1, 29
OUTPUTXBAR5 Output X-BAR Output 5 O 28, 7 1, 84 2, 57 2, 57 3, 52
OUTPUTXBAR6 Output X-BAR Output 6 O 29, 9 100, 90 1, 62 1, 62 2, 56
OUTPUTXBAR7 Output X-BAR Output 7 O 11, 16, 30 52, 54, 98 31, 33 31, 33 28, 30
OUTPUTXBAR8 Output X-BAR Output 8 O 17, 31 55, 99 34 34 31
PMBUSA_ALERT PMBus-A Open-Drain Bidirectional Alert Signal I/OD 13, 27, 37 50, 59, 61 37 29, 37 26, 34
PMBUSA_CTL PMBus-A Control Signal I 12, 18, 26, 35 51, 58, 63, 68 39, 41 30, 39, 41 27, 36, 38
PMBUSA_SCL PMBus-A Open-Drain Bidirectional Clock I/OD 15, 16, 24, 3, 35 54, 56, 63, 76, 95 33, 35, 39, 49 33, 35, 39, 49 30, 32, 36, 44
PMBUSA_SDA PMBus-A Open-Drain Bidirectional Data I/OD 14, 17, 2, 25, 34, 40 55, 57, 77, 85, 94, 96 34, 50 34, 50 31, 45
SCIA_RX SCI-A Receive Data I 17, 25, 28, 3, 35, 9 1, 55, 57, 63, 76, 90 2, 34, 39, 49, 62 2, 34, 39, 49, 62 3, 31, 36, 44, 56
SCIA_TX SCI-A Transmit Data O 16, 2, 24, 29, 37, 8 100, 54, 56, 61, 74, 77 1, 33, 35, 37, 47, 50 1, 33, 35, 37, 47, 50 2, 30, 32, 34, 42, 45
SCIB_RX SCI-B Receive Data I 11, 13, 15, 57 50, 52, 66, 95 31 29, 31 26, 28
SCIB_TX SCI-B Transmit Data O 10, 12, 14, 18, 22, 40, 56, 9 51, 65, 68, 83, 85, 90, 93, 96 41, 56, 62, 63 30, 41, 56, 62, 63 27, 38, 51, 56
SD1_C1 SDFM-1 Channel 1 Clock Input I 17, 25 55, 57 34 34 31
SD1_C2 SDFM-1 Channel 2 Clock Input I 27 59
SD1_C3 SDFM-1 Channel 3 Clock Input I 29, 33, 57 100, 53, 66 1, 32 1, 32 2, 29
SD1_C4 SDFM-1 Channel 4 Clock Input I 31, 59 92, 99
SD1_D1 SDFM-1 Channel 1 Data Input I 16, 24 54, 56 33, 35 33, 35 30, 32
SD1_D2 SDFM-1 Channel 2 Data Input I 18, 26 58, 68 41 41 38
SD1_D3 SDFM-1 Channel 3 Data Input I 28, 32, 56 1, 64, 65 2, 40 2, 40 3, 37
SD1_D4 SDFM-1 Channel 4 Data Input I 22, 30, 58 67, 83, 98 56 56 51
SPIA_CLK SPI-A Clock I/O 18, 3, 56, 9 65, 68, 76, 90 41, 49, 62 41, 49, 62 38, 44, 56
SPIA_SIMO SPI-A Slave In, Master Out (SIMO) I/O 16, 8 54, 74 33, 47 33, 47 30, 42
SPIA_SOMI SPI-A Slave Out, Master In (SOMI) I/O 10, 17 55, 93 34, 63 34, 63 31
SPIA_STE SPI-A Slave Transmit Enable (STE) I/O 11, 5, 57 52, 66, 89 31, 61 31, 61 28, 55
SPIB_CLK SPI-B Clock I/O 14, 22, 26, 28, 32, 58 1, 58, 64, 67, 83, 96 2, 40, 56 2, 40, 56 3, 37, 51
SPIB_SIMO SPI-B Slave In, Master Out (SIMO) I/O 24, 30, 56, 7 56, 65, 84, 98 35, 57 35, 57 32, 52
SPIB_SOMI SPI-B Slave Out, Master In (SOMI) I/O 25, 31, 57, 6 57, 66, 97, 99 64 64 1
SPIB_STE SPI-B Slave Transmit Enable (STE) I/O 15, 27, 29, 33, 59 100, 53, 59, 92, 95 1, 32 1, 32 2, 29
SYNCOUT External ePWM Synchronization Pulse O 6 97 64 64 1
TDI JTAG Test Data Input (TDI) - TDI is the default mux selection for the pin. The internal pullup is disabled by default. The internal pullup should be enabled or an external pullup added on the board if this pin is used as JTAG TDI to avoid a floating input. I 35 63 39 39 36
TDO JTAG Test Data Output (TDO) - TDO is the default mux selection for the pin. The internal pullup is disabled by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this pin floating; the internal pullup should be enabled or an external pullup added on the board to avoid a floating GPIO input. O 37 61 37 37 34
VFBSW Internal DC-DC regulator feedback signal. If the internal DC-DC regulator is used, tie this pin to the node where L(VSW) connects to the VDD rail (as close as possible to the device). - 22 83 56 56 51
VSW Switching output of the internal DC-DC regulator - 23 81 54 54 49
X2 Crystal oscillator output I/O 18 68 41 41 38
XCLKOUT External Clock Output. This pin outputs a divided-down version of a chosen clock signal from within the device. O 16, 18 54, 68 33, 41 33, 41 30, 38