Table 5-32 External Interrupt Switching Characteristics(1) over recommended operating conditions (unless otherwise noted)
||Delay time, INT low/high to interrupt-vector fetch(2)
||tw(IQSW) + 14tc(SYSCLK)
||tw(IQSW) + tw(SP) + 14tc(SYSCLK)
For an explanation of the input qualifier parameters, see Table 5-30
(2) This assumes that the ISR is in a single-cycle memory.
Figure 5-25 External Interrupt Timing