SPRS945E January   2017  – April 2020 TMS320F280040 , TMS320F280040C , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280048 , TMS320F280048C , TMS320F280049 , TMS320F280049C

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 Analog Signals
      2. 4.3.2 Digital Signals
      3. 4.3.3 Power and Ground
      4. 4.3.4 Test, JTAG, and Reset
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 4.4.3 GPIO Input X-BAR
      4. 4.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 4.5 Pins With Internal Pullup and Pulldown
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 System Current Consumption (External Supply)
      2. Table 5-2 System Current Consumption (Internal VREG)
      3. Table 5-3 System Current Consumption (DCDC)
      4. 5.5.1     Operating Mode Test Description
      5. 5.5.2     Current Consumption Graphs
      6. 5.5.3     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PZ Package
      2. 5.7.2 PM Package
      3. 5.7.3 RSH Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  System
      1. 5.9.1 Power Management
        1. 5.9.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 5.9.1.2 Internal 1.2-V Switching Regulator (DC-DC)
          1. 5.9.1.2.1 PCB Layout and Component Guidelines
            1. Table 5-8 Recommended External Components
        3. 5.9.1.3 Deciding Between the LDO and the DC-DC
        4. 5.9.1.4 Power Sequencing
        5. 5.9.1.5 Power-On Reset (POR)
        6. 5.9.1.6 Brownout Reset (BOR)
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Sources
        2. 5.9.2.2 Reset Electrical Data and Timing
          1. Table 5-10 Reset (XRSn) Timing Requirements
          2. Table 5-11 Reset (XRSn) Switching Characteristics
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1 Clock Sources
        2. 5.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-13 Input Clock Frequency
            2. Table 5-14 XTAL Oscillator Characteristics
            3. Table 5-15 X1 Timing Requirements
            4. Table 5-16 PLL Lock Times
          2. 5.9.3.2.2 Internal Clock Frequencies
            1. Table 5-17 Internal Clock Frequencies
          3. 5.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-18 XCLKOUT Switching Characteristics
        3. 5.9.3.3 Input Clocks and PLLs
        4. 5.9.3.4 Crystal Oscillator
          1. Table 5-19 Crystal Oscillator Parameters
          2. Table 5-21 Crystal Oscillator Electrical Characteristics
        5. 5.9.3.5 Internal Oscillators
          1. Table 5-22 INTOSC Characteristics
      4. 5.9.4 Flash Parameters
      5. 5.9.5 Emulation/JTAG
        1. 5.9.5.1 JTAG Electrical Data and Timing
          1. Table 5-25 JTAG Timing Requirements
          2. Table 5-26 JTAG Switching Characteristics
        2. 5.9.5.2 cJTAG Electrical Data and Timing
          1. Table 5-27 cJTAG Timing Requirements
          2. Table 5-28 cJTAG Switching Characteristics
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO – Output Timing
          1. Table 5-29 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO – Input Timing
          1. Table 5-30 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
      7. 5.9.7 Interrupts
        1. 5.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-31 External Interrupt Timing Requirements
          2. Table 5-32 External Interrupt Switching Characteristics
      8. 5.9.8 Low-Power Modes
        1. 5.9.8.1 Clock-Gating Low-Power Modes
        2. 5.9.8.2 Low-Power Mode Wake-up Timing
          1. Table 5-34 IDLE Mode Timing Requirements
          2. Table 5-35 IDLE Mode Switching Characteristics
          3. Table 5-36 HALT Mode Timing Requirements
          4. Table 5-37 HALT Mode Switching Characteristics
    10. 5.10 Analog Peripherals
      1. 5.10.1 Analog-to-Digital Converter (ADC)
        1. 5.10.1.1 ADC Configurability
          1. 5.10.1.1.1 Signal Mode
        2. 5.10.1.2 ADC Electrical Data and Timing
          1. Table 5-41 ADC Operating Conditions
          2. Table 5-42 ADC Characteristics
          3. 5.10.1.2.1 ADC Input Model
          4. 5.10.1.2.2 ADC Timing Diagrams
      2. 5.10.2 Programmable Gain Amplifier (PGA)
        1. 5.10.2.1 PGA Electrical Data and Timing
          1. Table 5-47 PGA Operating Conditions
          2. Table 5-48 PGA Characteristics
          3. 5.10.2.1.1 PGA Typical Characteristics Graphs
      3. 5.10.3 Temperature Sensor
        1. 5.10.3.1 Temperature Sensor Electrical Data and Timing
          1. Table 5-49 Temperature Sensor Characteristics
      4. 5.10.4 Buffered Digital-to-Analog Converter (DAC)
        1. 5.10.4.1 Buffered DAC Electrical Data and Timing
          1. Table 5-50 Buffered DAC Operating Conditions
          2. Table 5-51 Buffered DAC Electrical Characteristics
          3. 5.10.4.1.1 Buffered DAC Illustrative Graphs
          4. 5.10.4.1.2 Buffered DAC Typical Characteristics Graphs
      5. 5.10.5 Comparator Subsystem (CMPSS)
        1. 5.10.5.1 CMPSS Electrical Data and Timing
          1. Table 5-52 Comparator Electrical Characteristics
          2. Table 5-53 CMPSS DAC Static Electrical Characteristics
          3. 5.10.5.1.1 CMPSS Illustrative Graphs
    11. 5.11 Control Peripherals
      1. 5.11.1 Enhanced Capture (eCAP)
        1. 5.11.1.1 eCAP Electrical Data and Timing
          1. Table 5-54 eCAP Timing Requirements
          2. Table 5-55 eCAP Switching Charcteristics
      2. 5.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
        1. 5.11.2.1 HRCAP Electrical Data and Timing
          1. Table 5-56 HRCAP Switching Characteristics
      3. 5.11.3 Enhanced Pulse Width Modulator (ePWM)
        1. 5.11.3.1 Control Peripherals Synchronization
        2. 5.11.3.2 ePWM Electrical Data and Timing
          1. Table 5-57 ePWM Timing Requirements
          2. Table 5-58 ePWM Switching Characteristics
          3. 5.11.3.2.1 Trip-Zone Input Timing
            1. Table 5-59 Trip-Zone Input Timing Requirements
        3. 5.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-60 External ADC Start-of-Conversion Switching Characteristics
      4. 5.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.11.4.1 HRPWM Electrical Data and Timing
          1. Table 5-61 High-Resolution PWM Characteristics
      5. 5.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.11.5.1 eQEP Electrical Data and Timing
          1. Table 5-62 eQEP Timing Requirements
          2. Table 5-63 eQEP Switching Characteristics
      6. 5.11.6 Sigma-Delta Filter Module (SDFM)
        1. 5.11.6.1 SDFM Electrical Data and Timing
          1. Table 5-64 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 5.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
          1. Table 5-65 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
    12. 5.12 Communications Peripherals
      1. 5.12.1 Controller Area Network (CAN)
      2. 5.12.2 Inter-Integrated Circuit (I2C)
        1. 5.12.2.1 I2C Electrical Data and Timing
          1. Table 5-66 I2C Timing Requirements
          2. Table 5-67 I2C Switching Characteristics
      3. 5.12.3 Power Management Bus (PMBus) Interface
        1. 5.12.3.1 PMBus Electrical Data and Timing
          1. Table 5-68 PMBus Electrical Characteristics
          2. Table 5-69 PMBus Fast Mode Switching Characteristics
          3. Table 5-70 PMBus Standard Mode Switching Characteristics
      4. 5.12.4 Serial Communications Interface (SCI)
      5. 5.12.5 Serial Peripheral Interface (SPI)
        1. 5.12.5.1 SPI Electrical Data and Timing
          1. 5.12.5.1.1 Non-High-Speed Master Mode Timings
            1. Table 5-71 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-72 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-73 SPI Master Mode Timing Requirements
          2. 5.12.5.1.2 Non-High-Speed Slave Mode Timings
            1. Table 5-74 SPI Slave Mode Switching Characteristics
            2. Table 5-75 SPI Slave Mode Timing Requirements
          3. 5.12.5.1.3 High-Speed Master Mode Timings
            1. Table 5-76 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-77 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-78 SPI High-Speed Master Mode Timing Requirements
          4. 5.12.5.1.4 High-Speed Slave Mode Timings
            1. Table 5-79 SPI High-Speed Slave Mode Switching Characteristics
            2. Table 5-80 SPI High-Speed Slave Mode Timing Requirements
      6. 5.12.6 Local Interconnect Network (LIN)
      7. 5.12.7 Fast Serial Interface (FSI)
        1. 5.12.7.1 FSI Transmitter
          1. 5.12.7.1.1 FSITX Electrical Data and Timing
            1. Table 5-81 FSITX Switching Characteristics
        2. 5.12.7.2 FSI Receiver
          1. 5.12.7.2.1 FSIRX Electrical Data and Timing
            1. Table 5-82 FSIRX Switching Characteristics
            2. Table 5-83 FSIRX Timing Requirements
        3. 5.12.7.3 FSI SPI Compatibility Mode
          1. 5.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. Table 5-84 FSITX SPI Signaling Mode Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 Control Law Accelerator (CLA) ROM Memory Map
      3. 6.3.3 Flash Memory Map
      4. 6.3.4 Peripheral Registers Memory Map
      5. 6.3.5 Memory Types
        1. 6.3.5.1 Dedicated RAM (Mx RAM)
        2. 6.3.5.2 Local Shared RAM (LSx RAM)
        3. 6.3.5.3 Global Shared RAM (GSx RAM)
        4. 6.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
      2. 6.6.2 Floating-Point Unit (FPU)
      3. 6.6.3 Trigonometric Math Unit (TMU)
      4. 6.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
    7. 6.7  Control Law Accelerator (CLA)
    8. 6.8  Direct Memory Access (DMA)
    9. 6.9  Boot ROM and Peripheral Booting
      1. 6.9.1 Configuring Alternate Boot Mode Select Pins
      2. 6.9.2 Configuring Alternate Boot Mode Options
      3. 6.9.3 GPIO Assignments
    10. 6.10 Dual Code Security Module
    11. 6.11 Watchdog
    12. 6.12 Configurable Logic Block (CLB)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Markings
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Support Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Flash Memory Map

On the F28004x devices, up to two flash banks (each 128KB [64KW]) are available. The flash banks are controlled by a single FMC (flash module controller). On the devices in which there is only one flash bank (F280041 and F280040), the code to program the flash should be executed out of RAM. On the devices in which there are two flash banks (F280049, F280048, and F280045), only one bank at a time can be programmed or erased. In the dual-bank devices, the code to program the flash can be executed from one flash bank to erase or program the other flash bank, or the code can be executed from RAM. There should not be any kind of access to the flash bank on which an erase/program operation is in progress. Table 6-3 lists the addresses of flash sectors for F280049, F280048, and F280045. Table 6-4 lists the addresses of flash sectors for F280041 and F280040.

Table 6-3 Addresses of Flash Sectors for F280049, F280048, and F280045

SECTOR SIZE START ADDRESS END ADDRESS
OTP SECTORS
TI OTP Bank 0 1K × 16 0x0007 0000 0x0007 03FF
User-configurable DCSM OTP Bank 0 1K × 16 0x0007 8000 0x0007 83FF
TI OTP Bank 1 1K × 16 0x0007 0400 0x0007 07FF
User-configurable DCSM OTP Bank 1 1K × 16 0x0007 8400 0x0007 87FF
BANK 0 SECTORS
Sector 0 4K × 16 0x0008 0000 0x0008 0FFF
Sector 1 4K × 16 0x0008 1000 0x0008 1FFF
Sector 2 4K × 16 0x0008 2000 0x0008 2FFF
Sector 3 4K × 16 0x0008 3000 0x0008 3FFF
Sector 4 4K × 16 0x0008 4000 0x0008 4FFF
Sector 5 4K × 16 0x0008 5000 0x0008 5FFF
Sector 6 4K × 16 0x0008 6000 0x0008 6FFF
Sector 7 4K × 16 0x0008 7000 0x0008 7FFF
Sector 8 4K × 16 0x0008 8000 0x0008 8FFF
Sector 9 4K × 16 0x0008 9000 0x0008 9FFF
Sector 10 4K × 16 0x0008 A000 0x0008 AFFF
Sector 11 4K × 16 0x0008 B000 0x0008 BFFF
Sector 12 4K × 16 0x0008 C000 0x0008 CFFF
Sector 13 4K × 16 0x0008 D000 0x0008 DFFF
Sector 14 4K × 16 0x0008 E000 0x0008 EFFF
Sector 15 4K × 16 0x0008 F000 0x0008 FFFF
BANK 1 SECTORS
Sector 0 4K × 16 0x0009 0000 0x0009 0FFF
Sector 1 4K × 16 0x0009 1000 0x0009 1FFF
Sector 2 4K × 16 0x0009 2000 0x0009 2FFF
Sector 3 4K × 16 0x0009 3000 0x0009 3FFF
Sector 4 4K × 16 0x0009 4000 0x0009 4FFF
Sector 5 4K × 16 0x0009 5000 0x0009 5FFF
Sector 6 4K × 16 0x0009 6000 0x0009 6FFF
Sector 7 4K × 16 0x0009 7000 0x0009 7FFF
Sector 8 4K × 16 0x0009 8000 0x0009 8FFF
Sector 9 4K × 16 0x0009 9000 0x0009 9FFF
Sector 10 4K × 16 0x0009 A000 0x0009 AFFF
Sector 11 4K × 16 0x0009 B000 0x0009 BFFF
Sector 12 4K × 16 0x0009 C000 0x0009 CFFF
Sector 13 4K × 16 0x0009 D000 0x0009 DFFF
Sector 14 4K × 16 0x0009 E000 0x0009 EFFF
Sector 15 4K × 16 0x0009 F000 0x0009 FFFF
FLASH ECC LOCATIONS
TI OTP ECC Bank 0 128 × 16 0x0107 0000 0x0107 007F
TI OTP ECC Bank 1 128 × 16 0x0107 0080 0x0107 00FF
User-configurable DCSM OTP ECC Bank 0 128 × 16 0x0107 1000 0x0107 107F
User-configurable DCSM OTP ECC Bank 1 128 × 16 0x0107 1080 0x0107 10FF
Flash ECC Bank 0 8K × 16 0x0108 0000 0x0108 1FFF
Flash ECC Bank 1 8K × 16 0x0108 2000 0x0108 3FFF

Table 6-4 Addresses of Flash Sectors for F280041 and F280040

SECTOR SIZE START ADDRESS END ADDRESS
OTP SECTORS
TI OTP Bank 0 1K × 16 0x0007 0000 0x0007 03FF
User-configurable DCSM OTP Bank 0 1K × 16 0x0007 8000 0x0007 83FF
BANK 0 SECTORS
Sector 0 4K × 16 0x0008 0000 0x0008 0FFF
Sector 1 4K × 16 0x0008 1000 0x0008 1FFF
Sector 2 4K × 16 0x0008 2000 0x0008 2FFF
Sector 3 4K × 16 0x0008 3000 0x0008 3FFF
Sector 4 4K × 16 0x0008 4000 0x0008 4FFF
Sector 5 4K × 16 0x0008 5000 0x0008 5FFF
Sector 6 4K × 16 0x0008 6000 0x0008 6FFF
Sector 7 4K × 16 0x0008 7000 0x0008 7FFF
Sector 8 4K × 16 0x0008 8000 0x0008 8FFF
Sector 9 4K × 16 0x0008 9000 0x0008 9FFF
Sector 10 4K × 16 0x0008 A000 0x0008 AFFF
Sector 11 4K × 16 0x0008 B000 0x0008 BFFF
Sector 12 4K × 16 0x0008 C000 0x0008 CFFF
Sector 13 4K × 16 0x0008 D000 0x0008 DFFF
Sector 14 4K × 16 0x0008 E000 0x0008 EFFF
Sector 15 4K × 16 0x0008 F000 0x0008 FFFF
FLASH ECC LOCATIONS
TI OTP ECC Bank 0 128 × 16 0x0107 0000 0x0107 007F
User-configurable DCSM OTP ECC Bank 0 128 × 16 0x0107 1000 0x0107 107F
Flash ECC Bank 0 8K × 16 0x0108 0000 0x0108 1FFF