Table 5-23 lists the minimum required Flash wait states with different clock sources and frequencies.
|CPUCLK (MHz)||EXTERNAL OSCILLATOR OR CRYSTAL||INTOSC1 OR INTOSC2|
|FLASH READ OR EXECUTE||PROGRAM, ERASE, BANK SLEEP, OR PUMP SLEEP||FLASH READ OR EXECUTE||PROGRAM, ERASE, BANK SLEEP, OR PUMP SLEEP (2)|
|97 < CPUCLK ≤ 100||4||4||5|
|80 < CPUCLK ≤ 97||4|
|77 < CPUCLK ≤ 80||3||3||4|
|60 < CPUCLK ≤ 77||3|
|58 < CPUCLK ≤ 60||2||2||3|
|40 < CPUCLK ≤ 58||2|
|38 < CPUCLK ≤ 40||1||1||2|
|20 < CPUCLK ≤ 38||1|
|19 < CPUCLK ≤ 20||0||0||1|
|CPUCLK ≤ 19||0|
The F28004x devices have an improved 128-bit prefetch buffer that provides high flash code execution efficiency across wait states. Figure 5-15 and Figure 5-16 illustrate typical efficiency across wait-state settings compared to previous-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer will depend on how many branches are present in application software. Two examples of linear code and if-then-else code are provided.
Table 5-24 lists the Flash parameters.
|Program Time(1)||128 data bits + 16 ECC bits||150||300||µs|
|EraseTime(2) at < 25 W/E cycles||8KB sector||15||100||ms|
|EraseTime(2) at 1000 W/E cycles||8KB sector||25||350||ms|
|EraseTime(2) at 2000 W/E cycles||8KB sector||30||600||ms|
|EraseTime(2) at 20K W/E cycles||8KB sector||120||4000||ms|
|Nwec Write/Erase Cycles||20000||cycles|
|tretention Data retention duration at TJ = 85oC||20||years|
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit word may only be programmed once per write/erase cycle.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-bit word may only be programmed once. The exceptions are: