The internal DC-DC regulator offers increased efficiency over the LDO for converting 3.3 V to 1.2 V. The internal DC-DC regulator is supplied by the VDDIO_SW pin and generates the 1.2 V required to power the VDD pins. To use the internal switching regulator, the core domain must power up initially using the internal LDO VREG supply (tie the VREGENZ pin low to VSS) and then transition to the DC-DC regulator through application software by setting the DCDCEN bit in the DCDCCTL register. VREGENZ must still be kept low after transition since it controls both the DC-DC and LDO. Tying VREGENZ high disables both the DC-DC and LDO. The DC-DC regulator also requires external components (inductor, input capacitance, and output capacitance). The output of internal DC-DC regulator is not internally fed to the VDD rail and requires an external connection. Figure 5-6 shows the schematic implementation.
The VDDIO_SW supply pin (VIN) requires a 3.3-V level voltage. A total input capacitance (CVDDIO_SW) of 20 µF is required on VDDIO_SW. Due to the capacitor specification requirements detailed in Table 5-6, two parallel 10-µF capacitors in parallel is the recommended configuration. Decoupling capacitors of 100 nF should also be placed on each VDD pin as close to the device as possible.
|VALUE AND VARIATION||VALUE AT SATURATION||DCR||RATED CURRENT||SATURATION CURRENT||TEMPERATURE|
|2.2 µH ± 20%||1.54 µH ± 20%||80 mΩ ± 25%||>1000 mA||>600 mA||–40°C to 125°C|
|VALUE AND VARIATION AT 0 V||VALUE AT 1.2 V||VALUE AT 125°C||ESR||RATED VOLTAGE||TEMPERATURE|
|10 µF ± 20%||10 µF ± 20%||8 µF ± 20%||<10 mΩ||4 V or 6.3 V||–40°C to 125°C|
|Input capacitor||8||10||12||µF||20% varaince, two such capacitors in parallel|
|Output capacitor||8||10||12||µF||20% varaince, two such capacitors in parallel|