SPRS945E January   2017  – April 2020 TMS320F280040 , TMS320F280040C , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280048 , TMS320F280048C , TMS320F280049 , TMS320F280049C

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1 Analog Signals
      2. 4.3.2 Digital Signals
      3. 4.3.3 Power and Ground
      4. 4.3.4 Test, JTAG, and Reset
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 4.4.3 GPIO Input X-BAR
      4. 4.4.4 GPIO Output X-BAR and ePWM X-BAR
    5. 4.5 Pins With Internal Pullup and Pulldown
    6. 4.6 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 System Current Consumption (External Supply)
      2. Table 5-2 System Current Consumption (Internal VREG)
      3. Table 5-3 System Current Consumption (DCDC)
      4. 5.5.1     Operating Mode Test Description
      5. 5.5.2     Current Consumption Graphs
      6. 5.5.3     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PZ Package
      2. 5.7.2 PM Package
      3. 5.7.3 RSH Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  System
      1. 5.9.1 Power Management
        1. 5.9.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 5.9.1.2 Internal 1.2-V Switching Regulator (DC-DC)
          1. 5.9.1.2.1 PCB Layout and Component Guidelines
            1. Table 5-8 Recommended External Components
        3. 5.9.1.3 Deciding Between the LDO and the DC-DC
        4. 5.9.1.4 Power Sequencing
        5. 5.9.1.5 Power-On Reset (POR)
        6. 5.9.1.6 Brownout Reset (BOR)
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Sources
        2. 5.9.2.2 Reset Electrical Data and Timing
          1. Table 5-10 Reset (XRSn) Timing Requirements
          2. Table 5-11 Reset (XRSn) Switching Characteristics
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1 Clock Sources
        2. 5.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-13 Input Clock Frequency
            2. Table 5-14 XTAL Oscillator Characteristics
            3. Table 5-15 X1 Timing Requirements
            4. Table 5-16 PLL Lock Times
          2. 5.9.3.2.2 Internal Clock Frequencies
            1. Table 5-17 Internal Clock Frequencies
          3. 5.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-18 XCLKOUT Switching Characteristics
        3. 5.9.3.3 Input Clocks and PLLs
        4. 5.9.3.4 Crystal Oscillator
          1. Table 5-19 Crystal Oscillator Parameters
          2. Table 5-21 Crystal Oscillator Electrical Characteristics
        5. 5.9.3.5 Internal Oscillators
          1. Table 5-22 INTOSC Characteristics
      4. 5.9.4 Flash Parameters
      5. 5.9.5 Emulation/JTAG
        1. 5.9.5.1 JTAG Electrical Data and Timing
          1. Table 5-25 JTAG Timing Requirements
          2. Table 5-26 JTAG Switching Characteristics
        2. 5.9.5.2 cJTAG Electrical Data and Timing
          1. Table 5-27 cJTAG Timing Requirements
          2. Table 5-28 cJTAG Switching Characteristics
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO – Output Timing
          1. Table 5-29 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO – Input Timing
          1. Table 5-30 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
      7. 5.9.7 Interrupts
        1. 5.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-31 External Interrupt Timing Requirements
          2. Table 5-32 External Interrupt Switching Characteristics
      8. 5.9.8 Low-Power Modes
        1. 5.9.8.1 Clock-Gating Low-Power Modes
        2. 5.9.8.2 Low-Power Mode Wake-up Timing
          1. Table 5-34 IDLE Mode Timing Requirements
          2. Table 5-35 IDLE Mode Switching Characteristics
          3. Table 5-36 HALT Mode Timing Requirements
          4. Table 5-37 HALT Mode Switching Characteristics
    10. 5.10 Analog Peripherals
      1. 5.10.1 Analog-to-Digital Converter (ADC)
        1. 5.10.1.1 ADC Configurability
          1. 5.10.1.1.1 Signal Mode
        2. 5.10.1.2 ADC Electrical Data and Timing
          1. Table 5-41 ADC Operating Conditions
          2. Table 5-42 ADC Characteristics
          3. 5.10.1.2.1 ADC Input Model
          4. 5.10.1.2.2 ADC Timing Diagrams
      2. 5.10.2 Programmable Gain Amplifier (PGA)
        1. 5.10.2.1 PGA Electrical Data and Timing
          1. Table 5-47 PGA Operating Conditions
          2. Table 5-48 PGA Characteristics
          3. 5.10.2.1.1 PGA Typical Characteristics Graphs
      3. 5.10.3 Temperature Sensor
        1. 5.10.3.1 Temperature Sensor Electrical Data and Timing
          1. Table 5-49 Temperature Sensor Characteristics
      4. 5.10.4 Buffered Digital-to-Analog Converter (DAC)
        1. 5.10.4.1 Buffered DAC Electrical Data and Timing
          1. Table 5-50 Buffered DAC Operating Conditions
          2. Table 5-51 Buffered DAC Electrical Characteristics
          3. 5.10.4.1.1 Buffered DAC Illustrative Graphs
          4. 5.10.4.1.2 Buffered DAC Typical Characteristics Graphs
      5. 5.10.5 Comparator Subsystem (CMPSS)
        1. 5.10.5.1 CMPSS Electrical Data and Timing
          1. Table 5-52 Comparator Electrical Characteristics
          2. Table 5-53 CMPSS DAC Static Electrical Characteristics
          3. 5.10.5.1.1 CMPSS Illustrative Graphs
    11. 5.11 Control Peripherals
      1. 5.11.1 Enhanced Capture (eCAP)
        1. 5.11.1.1 eCAP Electrical Data and Timing
          1. Table 5-54 eCAP Timing Requirements
          2. Table 5-55 eCAP Switching Charcteristics
      2. 5.11.2 High-Resolution Capture Submodule (HRCAP6–HRCAP7)
        1. 5.11.2.1 HRCAP Electrical Data and Timing
          1. Table 5-56 HRCAP Switching Characteristics
      3. 5.11.3 Enhanced Pulse Width Modulator (ePWM)
        1. 5.11.3.1 Control Peripherals Synchronization
        2. 5.11.3.2 ePWM Electrical Data and Timing
          1. Table 5-57 ePWM Timing Requirements
          2. Table 5-58 ePWM Switching Characteristics
          3. 5.11.3.2.1 Trip-Zone Input Timing
            1. Table 5-59 Trip-Zone Input Timing Requirements
        3. 5.11.3.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-60 External ADC Start-of-Conversion Switching Characteristics
      4. 5.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.11.4.1 HRPWM Electrical Data and Timing
          1. Table 5-61 High-Resolution PWM Characteristics
      5. 5.11.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.11.5.1 eQEP Electrical Data and Timing
          1. Table 5-62 eQEP Timing Requirements
          2. Table 5-63 eQEP Switching Characteristics
      6. 5.11.6 Sigma-Delta Filter Module (SDFM)
        1. 5.11.6.1 SDFM Electrical Data and Timing
          1. Table 5-64 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 5.11.6.2 SDFM Electrical Data and Timing (Synchronized GPIO)
          1. Table 5-65 SDFM Timing Requirements When Using Synchronized GPIO (SYNC) Option
    12. 5.12 Communications Peripherals
      1. 5.12.1 Controller Area Network (CAN)
      2. 5.12.2 Inter-Integrated Circuit (I2C)
        1. 5.12.2.1 I2C Electrical Data and Timing
          1. Table 5-66 I2C Timing Requirements
          2. Table 5-67 I2C Switching Characteristics
      3. 5.12.3 Power Management Bus (PMBus) Interface
        1. 5.12.3.1 PMBus Electrical Data and Timing
          1. Table 5-68 PMBus Electrical Characteristics
          2. Table 5-69 PMBus Fast Mode Switching Characteristics
          3. Table 5-70 PMBus Standard Mode Switching Characteristics
      4. 5.12.4 Serial Communications Interface (SCI)
      5. 5.12.5 Serial Peripheral Interface (SPI)
        1. 5.12.5.1 SPI Electrical Data and Timing
          1. 5.12.5.1.1 Non-High-Speed Master Mode Timings
            1. Table 5-71 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-72 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-73 SPI Master Mode Timing Requirements
          2. 5.12.5.1.2 Non-High-Speed Slave Mode Timings
            1. Table 5-74 SPI Slave Mode Switching Characteristics
            2. Table 5-75 SPI Slave Mode Timing Requirements
          3. 5.12.5.1.3 High-Speed Master Mode Timings
            1. Table 5-76 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 5-77 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 5-78 SPI High-Speed Master Mode Timing Requirements
          4. 5.12.5.1.4 High-Speed Slave Mode Timings
            1. Table 5-79 SPI High-Speed Slave Mode Switching Characteristics
            2. Table 5-80 SPI High-Speed Slave Mode Timing Requirements
      6. 5.12.6 Local Interconnect Network (LIN)
      7. 5.12.7 Fast Serial Interface (FSI)
        1. 5.12.7.1 FSI Transmitter
          1. 5.12.7.1.1 FSITX Electrical Data and Timing
            1. Table 5-81 FSITX Switching Characteristics
        2. 5.12.7.2 FSI Receiver
          1. 5.12.7.2.1 FSIRX Electrical Data and Timing
            1. Table 5-82 FSIRX Switching Characteristics
            2. Table 5-83 FSIRX Timing Requirements
        3. 5.12.7.3 FSI SPI Compatibility Mode
          1. 5.12.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. Table 5-84 FSITX SPI Signaling Mode Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 Control Law Accelerator (CLA) ROM Memory Map
      3. 6.3.3 Flash Memory Map
      4. 6.3.4 Peripheral Registers Memory Map
      5. 6.3.5 Memory Types
        1. 6.3.5.1 Dedicated RAM (Mx RAM)
        2. 6.3.5.2 Local Shared RAM (LSx RAM)
        3. 6.3.5.3 Global Shared RAM (GSx RAM)
        4. 6.3.5.4 CLA Message RAM (CLA MSGRAM)
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Embedded Real-Time Analysis and Diagnostic (ERAD)
      2. 6.6.2 Floating-Point Unit (FPU)
      3. 6.6.3 Trigonometric Math Unit (TMU)
      4. 6.6.4 Viterbi, Complex Math and CRC Unit (VCU-I)
    7. 6.7  Control Law Accelerator (CLA)
    8. 6.8  Direct Memory Access (DMA)
    9. 6.9  Boot ROM and Peripheral Booting
      1. 6.9.1 Configuring Alternate Boot Mode Select Pins
      2. 6.9.2 Configuring Alternate Boot Mode Options
      3. 6.9.3 GPIO Assignments
    10. 6.10 Dual Code Security Module
    11. 6.11 Watchdog
    12. 6.12 Configurable Logic Block (CLB)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Markings
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Support Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Peripheral Registers Memory Map

Table 6-5 lists the peripheral registers.

Table 6-5 Peripheral Registers Memory Map

REGISTER STRUCTURE NAME START ADDRESS END ADDRESS PIPELINE
PROTECTION(1)
CLA ACCESS DMA ACCESS
Peripheral Frame 0
AdcaResultRegs(2) ADC_RESULT_REGS 0x0000 0B00 0x0000 0B1F Yes Yes
AdcbResultRegs(2) ADC_RESULT_REGS 0x0000 0B20 0x0000 0B3F Yes Yes
AdccResultRegs(2) ADC_RESULT_REGS 0x0000 0B40 0x0000 0B5F Yes Yes
Cla1OnlyRegs CLA_ONLY_REGS 0x0000 0C00 0x0000 0CFF Yes - CLA only no CPU access
CpuTimer0Regs CPUTIMER_REGS 0x0000 0C00 0x0000 0C07
CpuTimer1Regs CPUTIMER_REGS 0x0000 0C08 0x0000 0C0F
CpuTimer2Regs CPUTIMER_REGS 0x0000 0C10 0x0000 0C17
PieCtrlRegs PIE_CTRL_REGS 0x0000 0CE0 0x0000 0CFF
Cla1SoftIntRegs CLA_SOFTINT_REGS 0x0000 0CE0 0x0000 0CFF Yes - CLA only no CPU access
DmaRegs DMA_REGS 0x0000 1000 0x0000 11FF
Cla1Regs CLA_REGS 0x0000 1400 0x0000 147F Yes
Peripheral Frame 1
EPwm1Regs EPWM_REGS 0x0000 4000 0x0000 40FF Yes Yes Yes
EPwm2Regs EPWM_REGS 0x0000 4100 0x0000 41FF Yes Yes Yes
EPwm3Regs EPWM_REGS 0x0000 4200 0x0000 42FF Yes Yes Yes
EPwm4Regs EPWM_REGS 0x0000 4300 0x0000 43FF Yes Yes Yes
EPwm5Regs EPWM_REGS 0x0000 4400 0x0000 44FF Yes Yes Yes
EPwm6Regs EPWM_REGS 0x0000 4500 0x0000 45FF Yes Yes Yes
EPwm7Regs EPWM_REGS 0x0000 4600 0x0000 46FF Yes Yes Yes
EPwm8Regs EPWM_REGS 0x0000 4700 0x0000 47FF Yes Yes Yes
EQep1Regs EQEP_REGS 0x0000 5100 0x0000 513F Yes Yes Yes
EQep2Regs EQEP_REGS 0x0000 5140 0x0000 517F Yes Yes Yes
ECap1Regs ECAP_REGS 0x0000 5200 0x0000 521F Yes Yes Yes
ECap2Regs ECAP_REGS 0x0000 5240 0x0000 525F Yes Yes Yes
ECap3Regs ECAP_REGS 0x0000 5280 0x0000 529F Yes Yes Yes
ECap4Regs ECAP_REGS 0x0000 52C0 0x0000 52DF Yes Yes Yes
ECap5Regs ECAP_REGS 0x0000 5300 0x0000 531F Yes Yes Yes
ECap6Regs ECAP_REGS 0x0000 5340 0x0000 535F Yes Yes Yes
Hrcap6Regs HRCAP_REGS 0x0000 5360 0x0000 537F Yes Yes Yes
ECap7Regs ECAP_REGS 0x0000 5380 0x0000 539F Yes Yes Yes
Hrcap7Regs HRCAP_REGS 0x0000 53A0 0x0000 53BF Yes Yes Yes
Pga1Regs PGA_REGS 0x0000 5B00 0x0000 5B0F Yes Yes Yes
Pga2Regs PGA_REGS 0x0000 5B10 0x0000 5B1F Yes Yes Yes
Pga3Regs PGA_REGS 0x0000 5B20 0x0000 5B2F Yes Yes Yes
Pga4Regs PGA_REGS 0x0000 5B30 0x0000 5B3F Yes Yes Yes
Pga5Regs PGA_REGS 0x0000 5B40 0x0000 5B4F Yes Yes Yes
Pga6Regs PGA_REGS 0x0000 5B50 0x0000 5B5F Yes Yes Yes
Pga7Regs PGA_REGS 0x0000 5B60 0x0000 5B6F Yes Yes Yes
DacaRegs DAC_REGS 0x0000 5C00 0x0000 5C0F Yes Yes Yes
DacbRegs DAC_REGS 0x0000 5C10 0x0000 5C1F Yes Yes Yes
Cmpss1Regs CMPSS_REGS 0x0000 5C80 0x0000 5C9F Yes Yes Yes
Cmpss2Regs CMPSS_REGS 0x0000 5CA0 0x0000 5CBF Yes Yes Yes
Cmpss3Regs CMPSS_REGS 0x0000 5CC0 0x0000 5CDF Yes Yes Yes
Cmpss4Regs CMPSS_REGS 0x0000 5CE0 0x0000 5CFF Yes Yes Yes
Cmpss5Regs CMPSS_REGS 0x0000 5D00 0x0000 5D1F Yes Yes Yes
Cmpss6Regs CMPSS_REGS 0x0000 5D20 0x0000 5D3F Yes Yes Yes
Cmpss7Regs CMPSS_REGS 0x0000 5D40 0x0000 5D5F Yes Yes Yes
Sdfm1Regs SDFM_REGS 0x0000 5E00 0x0000 5E7F Yes Yes Yes
Peripheral Frame 2
SpiaRegs(4) SPI_REGS 0x0000 6100 0x0000 610F Yes Yes Yes
SpibRegs(4) SPI_REGS 0x0000 6110 0x0000 611F Yes Yes Yes
PmbusaRegs PMBUS_REGS 0x0000 6400 0x0000 641F Yes Yes Yes
FsiTxaRegs FSI_TX_REGS 0x0000 6600 0x0000 667F Yes Yes Yes
FsiRxaRegs FSI_RX_REGS 0x0000 6680 0x0000 66FF Yes Yes Yes
Peripheral Frame 3
AdcaRegs ADC_REGS 0x0000 7400 0x0000 747F Yes Yes
AdcbRegs ADC_REGS 0x0000 7480 0x0000 74FF Yes Yes
AdccRegs ADC_REGS 0x0000 7500 0x0000 757F Yes Yes
Peripheral Frame 4
InputXbarRegs INPUT_XBAR_REGS 0x0000 7900 0x0000 791F Yes
XbarRegs XBAR_REGS 0x0000 7920 0x0000 793F Yes
SyncSocRegs SYNC_SOC_REGS 0x0000 7940 0x0000 794F Yes
DmaClaSrcSelRegs DMA_CLA_SRC_SEL_REGS 0x0000 7980 0x0000 79BF Yes
EPwmXbarRegs EPWM_XBAR_REGS 0x0000 7A00 0x0000 7A3F Yes
OutputXbarRegs OUTPUT_XBAR_REGS 0x0000 7A80 0x0000 7ABF Yes
GpioCtrlRegs GPIO_CTRL_REGS 0x0000 7C00 0x0000 7EFF Yes
GpioDataRegs(3) GPIO_DATA_REGS 0x0000 7F00 0x0000 7FFF Yes Yes
Peripheral Frame 5
DevCfgRegs DEV_CFG_REGS 0x0005 D000 0x0005 D17F Yes
ClkCfgRegs CLK_CFG_REGS 0x0005 D200 0x0005 D2FF Yes
CpuSysRegs CPU_SYS_REGS 0x0005 D300 0x0005 D3FF Yes
PeriphAcRegs PERIPH_AC_REGS 0x0005 D500 0x0005 D6FF Yes
AnalogSubsysRegs ANALOG_SUBSYS_REGS 0x0005 D700 0x0005 D7FF Yes
Peripheral Frame 6
EnhancedDebugGlobalRegs ERAD_GLOBAL_REGS 0x0005 E800 0x0005 E80A
EnhancedDebugHWBP1Regs ERAD_HWBP_REGS 0x0005 E900 0x0005 E907
EnhancedDebugHWBP2Regs ERAD_HWBP_REGS 0x0005 E908 0x0005 E90F
EnhancedDebugHWBP3Regs ERAD_HWBP_REGS 0x0005 E910 0x0005 E917
EnhancedDebugHWBP4Regs ERAD_HWBP_REGS 0x0005 E918 0x0005 E91F
EnhancedDebugHWBP5Regs ERAD_HWBP_REGS 0x0005 E920 0x0005 E927
EnhancedDebugHWBP6Regs ERAD_HWBP_REGS 0x0005 E928 0x0005 E92F
EnhancedDebugHWBP7Regs ERAD_HWBP_REGS 0x0005 E930 0x0005 E937
EnhancedDebugHWBP8Regs ERAD_HWBP_REGS 0x0005 E938 0x0005 E93F
EnhancedDebugCounter1Regs ERAD_COUNTER_REGS 0x0005 E980 0x0005 E98F
EnhancedDebugCounter2Regs ERAD_COUNTER_REGS 0x0005 E990 0x0005 E99F
EnhancedDebugCounter3Regs ERAD_COUNTER_REGS 0x0005 E9A0 0x0005 E9AF
EnhancedDebugCounter4Regs ERAD_COUNTER_REGS 0x0005 E9B0 0x0005 E9BF
DcsmBank0Z1Regs DCSM_BANK0_Z1_REGS 0x0005 F000 0x0005 F022 Yes
DcsmBank0Z2Regs DCSM_BANK0_Z2_REGS 0x0005 F040 0x0005 F062 Yes
DcsmBank1Z1Regs DCSM_BANK1_Z1_REGS 0x0005 F100 0x0005 F122 Yes
DcsmBank1Z2Regs DCSM_BANK1_Z2_REGS 0x0005 F140 0x0005 F162 Yes
DcsmCommonRegs DCSM_COMMON_REGS 0x0005 F070 0x0005 F07F Yes
DcsmCommon2Regs DCSM_COMMON_REGS 0x0005 F080 0x0005 F087 Yes
MemCfgRegs MEM_CFG_REGS 0x0005 F400 0x0005 F47F Yes
AccessProtectionRegs ACCESS_PROTECTION_REGS 0x0005 F4C0 0x0005 F4FF Yes
MemoryErrorRegs MEMORY_ERROR_REGS 0x0005 F500 0x0005 F53F Yes
Flash0CtrlRegs FLASH_CTRL_REGS 0x0005 F800 0x0005 FAFF Yes
Flash0EccRegs FLASH_ECC_REGS 0x0005 FB00 0x0005 FB3F Yes
Peripheral Frame 7
CanaRegs CAN_REGS 0x0004 8000 0x0004 87FF Yes Yes
CanbRegs CAN_REGS 0x0004 A000 0x0004 A7FF Yes Yes
RomPrefetchRegs ROM_PREFETCH_REGS 0x0005 E608 0x0005 E609 Yes
DccRegs DCC_REGS 0x0005 E700 0x0005 E73F Yes
Peripheral Frame 8
LinaRegs LIN_REGS 0x0000 6A00 0x0000 6AFF Yes Yes Yes
Peripheral Frame 9
WdRegs(4) WD_REGS 0x0000 7000 0x0000 703F Yes
NmiIntruptRegs(4) NMI_INTRUPT_REGS 0x0000 7060 0x0000 706F Yes
XintRegs(4) XINT_REGS 0x0000 7070 0x0000 707F Yes
SciaRegs(4) SCI_REGS 0x0000 7200 0x0000 720F Yes
ScibRegs(4) SCI_REGS 0x0000 7210 0x0000 721F Yes
I2caRegs(4) I2C_REGS 0x0000 7300 0x0000 733F Yes
The CPU (not applicable for CLA or DMA) contains a write-followed-by-read protection mode to ensure that any read operation that follows a write operation within a protected address range is executed as written by delaying the read operation until the write is initiated.
ADC result register has no arbitration. Each master can access any ADC result register without any arbitration.
Both CPU and CLA have their own copy of GPIO_DATA_REGS, and hence, no arbitration is required between CPU and CLA. For more details, see the General-Purpose Input/Output (GPIO) chapter of the TMS320F28004x Microcontrollers Technical Reference Manual.
Registers with 16-bit access only.