Signal Pin Requirements: Before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).
VDDIO, VDDIO_SW, and VDDA Requirements: The 3.3-V supplies VDDIO, VDDIO_SW, and VDDA should be powered up together and kept within 0.3 V of each other during functional operation.
VDD Requirements: When VREGENZ is tied to VSS, the VDD sequencing requirements are handled by the device.
When using an external source for VDD (VREGENZ tied to VDDIO), VDDIO and VDD must be powered on and off at the same time. VDDIO should not be powered on when VDD is off. During the ramp, VDD should be kept no more than 0.3 V above VDDIO.
For applications not tying VREGENZ to VSS and not powering VDDIO and VDD at the same time, see the "INTOSC: VDDIO Powered Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F28004x MCUs Silicon Errata.