The C28x with VCU (C28x+VCU) processor extends the capabilities of the C28x fixed-point or floating-point CPU by adding registers and instructions to support the following algorithm types:
Viterbi decoding is commonly used in baseband communications applications. The viterbi decode algorithm consists of three main parts: branch metric calculations, compare-select (viterbi butterfly), and a traceback operation. Table 6-11 lists a summary of the VCU-I performance for each of these operations.
|VITERBI OPERATION||VCU CYCLES|
|Branch Metric Calculation (code rate = 1/2)||1|
|Branch Metric Calculation (code rate = 1/3)||2p|
|Viterbi Butterfly (add-compare-select)||2 (1)|
|Traceback per Stage||3 (2)|
CRC algorithms provide a straightforward method for verifying data integrity over large data blocks, communication packets, or code sections. The C28x+VCU can perform 8-, 16-, and 32-bit CRCs. For example, the VCU can compute the CRC for a block length of 10 bytes in 10 cycles. A CRC result register contains the current CRC which is updated whenever a CRC instruction is executed.
Complex math is used in many applications; a few of which are:
The complex FFT is used in spread spectrum communications, as well as many signal processing algorithms.
Complex filters improve data reliability, transmission distance, and power efficiency. The C28x+VCU can perform a complex I and Q multiply with coefficients (four multiplies) in a single cycle. In addition, the C28x+VCU can read/write the real and imaginary parts of 16-bit complex data to memory in a single cycle.
Table 6-12 lists a summary of a few complex math operations enabled by the VCU.
|COMPLEX MATH OPERATION||VCU CYCLES||NOTES|
|Add or Subtract||1||32 ± 32 = 32-bit (Useful for filters)|
|Add or Subtract||1||16 ± 32 = 15-bit (Useful for FFT)|
|Multiply||2p||16 × 16 = 32-bit|
|Multiply and Accumulate (MAC)||2p||32 + 32 = 32-bit, 16 × 16 = 32-bit|
|RPT MAC||2p+N||Repeat MAC. Single cycle after the first operation.|