SPRS230P October   2003  – February 2021 TMS320F2801 , TMS320F28015 , TMS320F28016 , TMS320F2802 , TMS320F2806 , TMS320F2808 , TMS320F2809

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings – Automotive
    3. 8.3  ESD Ratings – Commercial
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Consumption Summary
      1. 8.5.1 TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      2. 8.5.2 TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      3. 8.5.3 TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      4. 8.5.4 TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      5. 8.5.5 Reducing Current Consumption
      6. 8.5.6 Current Consumption Graphs
    6. 8.6  Electrical Characteristics
    7. 8.7  Thermal Resistance Characteristics for F280x 100-Ball GGM Package
    8. 8.8  Thermal Resistance Characteristics for F280x 100-Pin PZ Package
    9. 8.9  Thermal Resistance Characteristics for C280x 100-Ball GGM Package
    10. 8.10 Thermal Resistance Characteristics for C280x 100-Pin PZ Package
    11. 8.11 Thermal Resistance Characteristics for F2809 100-Ball GGM Package
    12. 8.12 Thermal Resistance Characteristics for F2809 100-Pin PZ Package
    13. 8.13 Thermal Design Considerations
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Timing Parameter Symbology
        1. 8.14.1.1 General Notes on Timing Parameters
        2. 8.14.1.2 Test Load Circuit
        3. 8.14.1.3 Device Clock Table
          1. 8.14.1.3.1 TMS320x280x Clock Table and Nomenclature (100-MHz Devices)
          2. 8.14.1.3.2 TMS320x280x/2801x Clock Table and Nomenclature (60-MHz Devices)
      2. 8.14.2 Power Sequencing
        1. 8.14.2.1 Reset ( XRS) Timing Requirements
      3. 8.14.3 Clock Requirements and Characteristics
        1. 8.14.3.1 Input Clock Frequency
        2. 8.14.3.2 XCLKIN Timing Requirements - PLL Enabled
        3. 8.14.3.3 XCLKIN Timing Requirements - PLL Disabled
        4. 8.14.3.4 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 8.14.4 Peripherals
        1. 8.14.4.1 General-Purpose Input/Output (GPIO)
          1. 8.14.4.1.1 GPIO - Output Timing
            1. 8.14.4.1.1.1 General-Purpose Output Switching Characteristics
          2. 8.14.4.1.2 GPIO - Input Timing
            1. 8.14.4.1.2.1 General-Purpose Input Timing Requirements
          3. 8.14.4.1.3 Sampling Window Width for Input Signals
          4. 8.14.4.1.4 Low-Power Mode Wakeup Timing
            1. 8.14.4.1.4.1 IDLE Mode Timing Requirements
            2. 8.14.4.1.4.2 IDLE Mode Switching Characteristics
            3. 8.14.4.1.4.3 STANDBY Mode Timing Requirements
            4. 8.14.4.1.4.4 STANDBY Mode Switching Characteristics
            5. 8.14.4.1.4.5 HALT Mode Timing Requirements
            6. 8.14.4.1.4.6 HALT Mode Switching Characteristics
        2. 8.14.4.2 Enhanced Control Peripherals
          1. 8.14.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. 8.14.4.2.1.1 ePWM Timing Requirements
            2. 8.14.4.2.1.2 ePWM Switching Characteristics
          2. 8.14.4.2.2 Trip-Zone Input Timing
            1. 8.14.4.2.2.1 Trip-Zone input Timing Requirements
          3. 8.14.4.2.3 High-Resolution PWM Timing
            1. 8.14.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = 60–100 MHz
          4. 8.14.4.2.4 Enhanced Capture (eCAP) Timing
            1. 8.14.4.2.4.1 Enhanced Capture (eCAP) Timing Requirement
            2. 8.14.4.2.4.2 eCAP Switching Characteristics
          5. 8.14.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. 8.14.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. 8.14.4.2.5.2 eQEP Switching Characteristics
          6. 8.14.4.2.6 ADC Start-of-Conversion Timing
            1. 8.14.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
        3. 8.14.4.3 External Interrupt Timing
          1. 8.14.4.3.1 External Interrupt Timing Requirements
          2. 8.14.4.3.2 External Interrupt Switching Characteristics
        4. 8.14.4.4 I2C Electrical Specification and Timing
          1. 8.14.4.4.1 I2C Timing
        5. 8.14.4.5 Serial Peripheral Interface (SPI) Timing
          1. 8.14.4.5.1 SPI Master Mode Timing
            1. 8.14.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0)
            2. 8.14.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1)
          2. 8.14.4.5.2 SPI Slave Mode Timing
            1. 8.14.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
            2. 8.14.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 8.14.5 Emulator Connection Without Signal Buffering for the DSP
      6. 8.14.6 Flash Timing
        1. 8.14.6.1 Flash Endurance for A and S Temperature Material
        2. 8.14.6.2 Flash Endurance for Q Temperature Material
        3. 8.14.6.3 Flash Parameters at 100-MHz SYSCLKOUT
        4. 8.14.6.4 Flash/OTP Access Timing
        5. 8.14.6.5 Flash Data Retention Duration
    15. 8.15 On-Chip Analog-to-Digital Converter
      1. 8.15.1 ADC Electrical Characteristics
      2. 8.15.2 ADC Power-Up Control Bit Timing
        1. 8.15.2.1 ADC Power-Up Delays
        2. 8.15.2.2 Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)
      3. 8.15.3 Definitions
      4. 8.15.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. 8.15.4.1 Sequential Sampling Mode Timing
      5. 8.15.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. 8.15.5.1 Simultaneous Sampling Mode Timing
      6. 8.15.6 Detailed Descriptions
    16. 8.16 Migrating From F280x Devices to C280x Devices
      1. 8.16.1 Migration Issues
    17. 8.17 ROM Timing (C280x only)
      1. 8.17.1 ROM/OTP Access Timing
  9. 9 Detailed Description
    1. 9.1 Brief Descriptions
      1. 9.1.1  C28x CPU
      2. 9.1.2  Memory Bus (Harvard Bus Architecture)
      3. 9.1.3  Peripheral Bus
      4. 9.1.4  Real-Time JTAG and Analysis
      5. 9.1.5  Flash
      6. 9.1.6  ROM
      7. 9.1.7  M0, M1 SARAMs
      8. 9.1.8  L0, L1, H0 SARAMs
      9. 9.1.9  Boot ROM
      10. 9.1.10 Security
      11. 9.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 9.1.12 External Interrupts (XINT1, XINT2, XNMI)
      13. 9.1.13 Oscillator and PLL
      14. 9.1.14 Watchdog
      15. 9.1.15 Peripheral Clocking
      16. 9.1.16 Low-Power Modes
      17. 9.1.17 Peripheral Frames 0, 1, 2 (PFn)
      18. 9.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 9.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 9.1.20 Control Peripherals
      21. 9.1.21 Serial Port Peripherals
    2. 9.2 Peripherals
      1. 9.2.1  32-Bit CPU-Timers 0/1/2
      2. 9.2.2  Enhanced PWM Modules (ePWM1/2/3/4/5/6)
      3. 9.2.3  Hi-Resolution PWM (HRPWM)
      4. 9.2.4  Enhanced CAP Modules (eCAP1/2/3/4)
      5. 9.2.5  Enhanced QEP Modules (eQEP1/2)
      6. 9.2.6  Enhanced Analog-to-Digital Converter (ADC) Module
        1. 9.2.6.1 ADC Connections if the ADC Is Not Used
        2. 9.2.6.2 ADC Registers
      7. 9.2.7  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      8. 9.2.8  Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
      9. 9.2.9  Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
      10. 9.2.10 Inter-Integrated Circuit (I2C)
      11. 9.2.11 GPIO MUX
    3. 9.3 Memory Maps
    4. 9.4 Register Map
      1. 9.4.1 Device Emulation Registers
    5. 9.5 Interrupts
      1. 9.5.1 External Interrupts
    6. 9.6 System Control
      1. 9.6.1 OSC and PLL Block
        1. 9.6.1.1 External Reference Oscillator Clock Option
        2. 9.6.1.2 PLL-Based Clock Module
        3. 9.6.1.3 Loss of Input Clock
      2. 9.6.2 Watchdog Block
    7. 9.7 Low-Power Modes Block
  10. 10Applications, Implementation, and Layout
    1. 10.1 TI Design or Reference Design
  11. 11Device and Documentation Support
    1. 11.1 Getting Started
    2. 11.2 Device and Development Support Tool Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PZ|100
Thermal pad, mechanical data (Package|Pins)
Orderable Information