The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
All four pins can be used as GPIO if the SPI module is not used.
Baud rate: 125 different programmable rates.
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.
The SPI port operation is configured and controlled by the registers listed in Table 6-32.
|NAME||ADDRESS||SIZE (x16)||EALLOW PROTECTED||DESCRIPTION(1)|
|SPICCR||0x7040||1||No||SPI-A Configuration Control Register|
|SPICTL||0x7041||1||No||SPI-A Operation Control Register|
|SPISTS||0x7042||1||No||SPI-A Status Register|
|SPIBRR||0x7044||1||No||SPI-A Baud Rate Register|
|SPIRXEMU||0x7046||1||No||SPI-A Receive Emulation Buffer Register|
|SPIRXBUF||0x7047||1||No||SPI-A Serial Input Buffer Register|
|SPITXBUF||0x7048||1||No||SPI-A Serial Output Buffer Register|
|SPIDAT||0x7049||1||No||SPI-A Serial Data Register|
|SPIFFTX||0x704A||1||No||SPI-A FIFO Transmit Register|
|SPIFFRX||0x704B||1||No||SPI-A FIFO Receive Register|
|SPIFFCT||0x704C||1||No||SPI-A FIFO Control Register|
|SPIPRI||0x704F||1||No||SPI-A Priority Control Register|
For more information on the SPI, see the Serial Peripheral Interface (SPI) chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.
Figure 6-28 is a block diagram of the SPI in slave mode.