SPRS523N November   2008  – June 2020 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28026 , TMS320F28026F , TMS320F28027 , TMS320F28027F

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2802x/F280200 Current Consumption at 40-MHz SYSCLKOUT
      2. Table 5-2 TMS320F2802x Current Consumption at 50-MHz SYSCLKOUT
      3. Table 5-3 TMS320F2802x Current Consumption at 60-MHz SYSCLKOUT
      4. 5.5.1     Reducing Current Consumption
      5. 5.5.2     Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PT Package
      2. 5.7.2 DA Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-5 Reset (XRS) Timing Requirements
      2. Table 5-6 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-7  2802x Clock Table and Nomenclature (40-MHz Devices)
        2. Table 5-8  2802x Clock Table and Nomenclature (50-MHz Devices)
        3. Table 5-9  2802x Clock Table and Nomenclature (60-MHz Devices)
        4. Table 5-10 Device Clocking Requirements/Characteristics
        5. Table 5-11 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-12 XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-13 XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-14 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-15 Flash/OTP Endurance for T Temperature Material
      2. Table 5-16 Flash/OTP Endurance for S Temperature Material
      3. Table 5-17 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-18 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-19 Flash Parameters at 50-MHz SYSCLKOUT
      6. Table 5-20 Flash Parameters at 40-MHz SYSCLKOUT
      7. Table 5-21 Flash Program/Erase Time
      8. Table 5-22 Flash/OTP Access Timing
      9. Table 5-23 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  Flash
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0 SARAM
      8. 6.1.8  Boot ROM
        1. 6.1.8.1 Emulation Boot
        2. 6.1.8.2 GetMode
        3. 6.1.8.3 Peripheral Pins Used by the Bootloader
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1–XINT3)
      12. 6.1.12 Internal Zero Pin Oscillators, Oscillator, and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG/BOR/POR
      1. 6.5.1 On-chip Voltage Regulator (VREG)
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 6.6.5 CPU Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-21 External Interrupt Timing Requirements
          2. Table 6-22 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Analog Block
        1. 6.9.1.1 Analog-to-Digital Converter (ADC)
          1. 6.9.1.1.1 Features
          2. 6.9.1.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-25 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.1.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-26  ADC Electrical Characteristics
            2. Table 6-27  ADC Power Modes
            3. 6.9.1.1.3.1 Internal Temperature Sensor
              1. Table 6-28 Temperature Sensor Coefficient
            4. 6.9.1.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-29 ADC Power-Up Delays
            5. 6.9.1.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.1.2 ADC MUX
        3. 6.9.1.3 Comparator Block
          1. 6.9.1.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-31 Electrical Characteristics of the Comparator/DAC
      2. 6.9.2  Detailed Descriptions
      3. 6.9.3  Serial Peripheral Interface (SPI) Module
        1. 6.9.3.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-33 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-34 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.3.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-35 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-36 SPI Slave Mode External Timing (Clock Phase = 1)
      4. 6.9.4  Serial Communications Interface (SCI) Module
      5. 6.9.5  Inter-Integrated Circuit (I2C)
        1. 6.9.5.1 I2C Electrical Data/Timing
          1. Table 6-39 I2C Timing Requirements
          2. Table 6-40 I2C Switching Characteristics
      6. 6.9.6  Enhanced PWM Modules (ePWM1/2/3/4)
        1. 6.9.6.1 ePWM Electrical Data/Timing
          1. Table 6-42 ePWM Timing Requirements
          2. Table 6-43 ePWM Switching Characteristics
        2. 6.9.6.2 Trip-Zone Input Timing
          1. Table 6-44 Trip-Zone Input Timing Requirements
      7. 6.9.7  High-Resolution PWM (HRPWM)
        1. 6.9.7.1 HRPWM Electrical Data/Timing
          1. Table 6-45 High-Resolution PWM Characteristics at SYSCLKOUT = 50 MHz–60 MHz
      8. 6.9.8  Enhanced Capture Module (eCAP1)
        1. 6.9.8.1 eCAP Electrical Data/Timing
          1. Table 6-47 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-48 eCAP Switching Characteristics
      9. 6.9.9  JTAG Port
      10. 6.9.10 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.10.1 GPIO Electrical Data/Timing
          1. 6.9.10.1.1 GPIO - Output Timing
            1. Table 6-54 General-Purpose Output Switching Characteristics
          2. 6.9.10.1.2 GPIO - Input Timing
            1. Table 6-55 General-Purpose Input Timing Requirements
          3. 6.9.10.1.3 Sampling Window Width for Input Signals
          4. 6.9.10.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-56 IDLE Mode Timing Requirements
            2. Table 6-57 IDLE Mode Switching Characteristics
            3. Table 6-58 STANDBY Mode Timing Requirements
            4. Table 6-59 STANDBY Mode Switching Characteristics
            5. Table 6-60 HALT Mode Timing Requirements
            6. Table 6-61 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Serial Peripheral Interface (SPI) Module

The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

  • Four external pins:
    • SPISOMI: SPI slave-output/master-input pin
    • SPISIMO: SPI slave-input/master-output pin
    • SPISTE: SPI slave transmit-enable pin
    • SPICLK: SPI serial-clock pin

NOTE

All four pins can be used as GPIO if the SPI module is not used.

  • Two operational modes: master and slave
  • Baud rate: 125 different programmable rates.

    TMS320F28027 TMS320F28027F TMS320F28026 TMS320F28026F TMS320F28023 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200 q_spibrr_des_prs230.gif
  • Data word length: 1 to 16 data bits
  • Four clocking schemes (controlled by clock polarity and clock phase bits) include:
    • Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
    • Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
    • Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
    • Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
  • Simultaneous receive and transmit operation (transmit function can be disabled in software)
  • Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
  • Nine SPI module control registers: In control register frame beginning at address 7040h.
  • NOTE

    All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced feature:

  • 4-level transmit/receive FIFO
  • Delayed transmit control
  • Bidirectional 3 wire SPI mode support

The SPI port operation is configured and controlled by the registers listed in Table 6-32.

Table 6-32 SPI-A Registers

NAME ADDRESS SIZE (x16) EALLOW PROTECTED DESCRIPTION(1)
SPICCR 0x7040 1 No SPI-A Configuration Control Register
SPICTL 0x7041 1 No SPI-A Operation Control Register
SPISTS 0x7042 1 No SPI-A Status Register
SPIBRR 0x7044 1 No SPI-A Baud Rate Register
SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register
SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register
SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register
SPIDAT 0x7049 1 No SPI-A Serial Data Register
SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register
SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register
SPIFFCT 0x704C 1 No SPI-A FIFO Control Register
SPIPRI 0x704F 1 No SPI-A Priority Control Register
Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.

For more information on the SPI, see the Serial Peripheral Interface (SPI) chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.

Figure 6-28 is a block diagram of the SPI in slave mode.

TMS320F28027 TMS320F28027F TMS320F28026 TMS320F28026F TMS320F28023 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200 fbd_spi_prs523.gif
SPISTE is driven low by the master for a slave device.
Figure 6-28 SPI Module Block Diagram (Slave Mode)