SPRS523N November   2008  – June 2020 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28026 , TMS320F28026F , TMS320F28027 , TMS320F28027F

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2802x/F280200 Current Consumption at 40-MHz SYSCLKOUT
      2. Table 5-2 TMS320F2802x Current Consumption at 50-MHz SYSCLKOUT
      3. Table 5-3 TMS320F2802x Current Consumption at 60-MHz SYSCLKOUT
      4. 5.5.1     Reducing Current Consumption
      5. 5.5.2     Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PT Package
      2. 5.7.2 DA Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-5 Reset (XRS) Timing Requirements
      2. Table 5-6 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-7  2802x Clock Table and Nomenclature (40-MHz Devices)
        2. Table 5-8  2802x Clock Table and Nomenclature (50-MHz Devices)
        3. Table 5-9  2802x Clock Table and Nomenclature (60-MHz Devices)
        4. Table 5-10 Device Clocking Requirements/Characteristics
        5. Table 5-11 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-12 XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-13 XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-14 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-15 Flash/OTP Endurance for T Temperature Material
      2. Table 5-16 Flash/OTP Endurance for S Temperature Material
      3. Table 5-17 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-18 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-19 Flash Parameters at 50-MHz SYSCLKOUT
      6. Table 5-20 Flash Parameters at 40-MHz SYSCLKOUT
      7. Table 5-21 Flash Program/Erase Time
      8. Table 5-22 Flash/OTP Access Timing
      9. Table 5-23 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  Flash
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0 SARAM
      8. 6.1.8  Boot ROM
        1. 6.1.8.1 Emulation Boot
        2. 6.1.8.2 GetMode
        3. 6.1.8.3 Peripheral Pins Used by the Bootloader
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1–XINT3)
      12. 6.1.12 Internal Zero Pin Oscillators, Oscillator, and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG/BOR/POR
      1. 6.5.1 On-chip Voltage Regulator (VREG)
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 6.6.5 CPU Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-21 External Interrupt Timing Requirements
          2. Table 6-22 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Analog Block
        1. 6.9.1.1 Analog-to-Digital Converter (ADC)
          1. 6.9.1.1.1 Features
          2. 6.9.1.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-25 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.1.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-26  ADC Electrical Characteristics
            2. Table 6-27  ADC Power Modes
            3. 6.9.1.1.3.1 Internal Temperature Sensor
              1. Table 6-28 Temperature Sensor Coefficient
            4. 6.9.1.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-29 ADC Power-Up Delays
            5. 6.9.1.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.1.2 ADC MUX
        3. 6.9.1.3 Comparator Block
          1. 6.9.1.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-31 Electrical Characteristics of the Comparator/DAC
      2. 6.9.2  Detailed Descriptions
      3. 6.9.3  Serial Peripheral Interface (SPI) Module
        1. 6.9.3.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-33 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-34 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.3.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-35 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-36 SPI Slave Mode External Timing (Clock Phase = 1)
      4. 6.9.4  Serial Communications Interface (SCI) Module
      5. 6.9.5  Inter-Integrated Circuit (I2C)
        1. 6.9.5.1 I2C Electrical Data/Timing
          1. Table 6-39 I2C Timing Requirements
          2. Table 6-40 I2C Switching Characteristics
      6. 6.9.6  Enhanced PWM Modules (ePWM1/2/3/4)
        1. 6.9.6.1 ePWM Electrical Data/Timing
          1. Table 6-42 ePWM Timing Requirements
          2. Table 6-43 ePWM Switching Characteristics
        2. 6.9.6.2 Trip-Zone Input Timing
          1. Table 6-44 Trip-Zone Input Timing Requirements
      7. 6.9.7  High-Resolution PWM (HRPWM)
        1. 6.9.7.1 HRPWM Electrical Data/Timing
          1. Table 6-45 High-Resolution PWM Characteristics at SYSCLKOUT = 50 MHz–60 MHz
      8. 6.9.8  Enhanced Capture Module (eCAP1)
        1. 6.9.8.1 eCAP Electrical Data/Timing
          1. Table 6-47 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-48 eCAP Switching Characteristics
      9. 6.9.9  JTAG Port
      10. 6.9.10 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.10.1 GPIO Electrical Data/Timing
          1. 6.9.10.1.1 GPIO - Output Timing
            1. Table 6-54 General-Purpose Output Switching Characteristics
          2. 6.9.10.1.2 GPIO - Input Timing
            1. Table 6-55 General-Purpose Input Timing Requirements
          3. 6.9.10.1.3 Sampling Window Width for Input Signals
          4. 6.9.10.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-56 IDLE Mode Timing Requirements
            2. Table 6-57 IDLE Mode Switching Characteristics
            3. Table 6-58 STANDBY Mode Timing Requirements
            4. Table 6-59 STANDBY Mode Switching Characteristics
            5. Table 6-60 HALT Mode Timing Requirements
            6. Table 6-61 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Table 4-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details. Inputs are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup.

NOTE

When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins could glitch during power up. This potential glitch will finish before the boot mode pins are read and will not affect boot behavior. If glitching is unacceptable in an application, 1.8 V could be supplied externally. Alternatively, adding a current-limiting resistor (for example, 470 Ω) in series with these pins and any external driver could be considered to limit the potential for degradation to the pin and/or external circuitry. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered before the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins before or with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.

Table 4-1 Signal Descriptions(1)

TERMINAL I/O/Z DESCRIPTION
NAME PT
PIN NO.
DA
PIN NO.
JTAG
TRST 2 16 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE:TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application. (↓)
TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup (↑)
TMS See GPIO36 I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑)
TDI See GPIO35 I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑)
TDO See GPIO37 O/Z See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.
(8-mA drive)
FLASH
TEST 30 38 I/O Test Pin. Reserved for TI. Must be left unconnected.
CLOCK
XCLKOUT See GPIO18 O/Z See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
XCLKIN See GPIO19 and GPIO38 I See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled through bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device.
X1 45 I On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND. (I)
X2 46 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
XRS 3 17 I/OD Device Reset (in) and Watchdog Reset (out). These devices have a built-in power-on reset (POR) and brown-out reset (BOR) circuitry. During a power-on or brown-out condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3F FFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain device with an internal pullup. (↑) If this pin is driven by an external device, it should be done using an open-drain device.
ADC, COMPARATOR, ANALOG I/O
ADCINA7 6 I ADC Group A, Channel 7 input
ADCINA6 4 18 I ADC Group A, Channel 6 input
AIO6 I/O Digital AIO 6
ADCINA4 5 19 I ADC Group A, Channel 4 input
COMP2A I Comparator Input 2A (available in 48-pin device only)
AIO4 I/O Digital AIO 4
ADCINA3 7 I ADC Group A, Channel 3 input
ADCINA2 9 20 I ADC Group A, Channel 2 input
COMP1A I Comparator Input 1A
AIO2 I/O Digital AIO 2
ADCINA1 8 I ADC Group A, Channel 1 input
ADCINA0 10 21 I ADC Group A, Channel 0 input
VREFHI I ADC External Reference High – only used when in ADC external reference mode. See Section 6.9.1.1, ADC.
ADCINB7 18 I ADC Group B, Channel 7 input
ADCINB6 17 26 I ADC Group B, Channel 6 input
AIO14 I/O Digital AIO 14
ADCINB4 16 25 I ADC Group B, Channel 4 input
COMP2B I Comparator Input 2B (available in 48-pin device only)
AIO12 I/O Digital AIO12
ADCINB3 15 I ADC Group B, Channel 3 input
ADCINB2 14 24 I ADC Group B, Channel 2 input
COMP1B I Comparator Input 1B
AIO10 I/O Digital AIO 10
ADCINB1 13 I ADC Group B, Channel 1 input
CPU AND I/O POWER
VDDA 11 22 Analog Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin.
VSSA 12 23 Analog Ground Pin
VREFLO I ADC External Reference Low (always tied to ground)
VDD 32 1 CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. Higher value capacitors may be used.
43 11
VDDIO 35 4 Digital I/O Buffers and Flash Memory Power Pin. Single supply source when VREG is enabled. Place a decoupling capacitor on this pin. The exact value should be determined by the system voltage regulation solution.
VSS 33 2 Digital Ground Pins
44 12
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ 34 3 I Internal VREG Enable/Disable. Pull low to enable the internal voltage regulator (VREG), pull high to disable VREG.
GPIO AND PERIPHERAL SIGNALS(2)
GPIO0 29 37 I/O/Z General-purpose input/output 0
EPWM1A O Enhanced PWM1 Output A and HRPWM channel
GPIO1 28 36 I/O/Z General-purpose input/output 1
EPWM1B O Enhanced PWM1 Output B
COMP1OUT O Direct output of Comparator 1
GPIO2 37 5 I/O/Z General-purpose input/output 2
EPWM2A O Enhanced PWM2 Output A and HRPWM channel
GPIO3 38 6 I/O/Z General-purpose input/output 3
EPWM2B O Enhanced PWM2 Output B
COMP2OUT O Direct output of Comparator 2 (available in 48-pin device only)
GPIO4 39 7 I/O/Z General-purpose input/output 4
EPWM3A O Enhanced PWM3 output A and HRPWM channel
GPIO5 40 8 I/O/Z General-purpose input/output 5
EPWM3B O Enhanced PWM3 output B
ECAP1 I/O Enhanced Capture input/output 1
GPIO6 41 9 I/O/Z General-purpose input/output 6
EPWM4A O Enhanced PWM4 output A and HRPWM channel
EPWMSYNCI I External ePWM sync pulse input
EPWMSYNCO O External ePWM sync pulse output
GPIO7 42 10 I/O/Z General-purpose input/output 7
EPWM4B O Enhanced PWM4 output B
SCIRXDA I SCI-A receive data
GPIO12 47 13 I/O/Z General-purpose input/output 12
TZ1 I Trip Zone input 1
SCITXDA O SCI-A transmit data
GPIO16 27 35 I/O/Z General-purpose input/output 16
SPISIMOA I/O SPI slave in, master out
TZ2 I Trip Zone input 2
GPIO17 26 34 I/O/Z General-purpose input/output 17
SPISOMIA I/O SPI-A slave out, master in
TZ3 I Trip zone input 3
GPIO18 24 32 I/O/Z General-purpose input/output 18
SPICLKA I/O SPI-A clock input/output
SCITXDA O SCI-A transmit
XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV
to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
GPIO19 25 33 I/O/Z General-purpose input/output 19
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if it is being used for the other periperhal functions
SPISTEA I/O SPI-A slave transmit enable input/output
SCIRXDA I SCI-A receive
ECAP1 I/O Enhanced Capture input/output 1
GPIO28 48 14 I/O/Z General-purpose input/output 28
SCIRXDA I SCI receive data
SDAA I/OD I2C data open-drain bidirectional port
TZ2 I Trip zone input 2
GPIO29 1 15 I/O/Z General-purpose input/output 29.
SCITXDA O SCI transmit data
SCLA I/OD I2C clock open-drain bidirectional port
TZ3 I Trip zone input 3
GPIO32 31 I/O/Z General-purpose input/output 32
SDAA I/OD I2C data open-drain bidirectional port
EPWMSYNCI I Enhanced PWM external sync pulse input
ADCSOCAO O ADC start-of-conversion A
GPIO33 36 I/O/Z General-Purpose Input/Output 33
SCLA I/OD I2C clock open-drain bidirectional port
EPWMSYNCO O Enhanced PWM external synch pulse output
ADCSOCBO O ADC start-of-conversion B
GPIO34 19 27 I/O/Z General-Purpose Input/Output 34
COMP2OUT O Direct output of Comparator 2. COMP2OUT signal is not available in the DA package.
GPIO35 20 28 I/O/Z General-Purpose Input/Output 35
TDI I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK
GPIO36 21 29 I/O/Z General-Purpose Input/Output 36
TMS I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK.
GPIO37 22 30 I/O/Z General-Purpose Input/Output 37
TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive)
GPIO38 23 31 I/O/Z General-Purpose Input/Output 38
TCK I JTAG test clock with internal pullup
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other functions.
I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the System Control chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual for details.