SPRS523N November   2008  – June 2020 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28026 , TMS320F28026F , TMS320F28027 , TMS320F28027F

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2802x/F280200 Current Consumption at 40-MHz SYSCLKOUT
      2. Table 5-2 TMS320F2802x Current Consumption at 50-MHz SYSCLKOUT
      3. Table 5-3 TMS320F2802x Current Consumption at 60-MHz SYSCLKOUT
      4. 5.5.1     Reducing Current Consumption
      5. 5.5.2     Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PT Package
      2. 5.7.2 DA Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-5 Reset (XRS) Timing Requirements
      2. Table 5-6 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-7  2802x Clock Table and Nomenclature (40-MHz Devices)
        2. Table 5-8  2802x Clock Table and Nomenclature (50-MHz Devices)
        3. Table 5-9  2802x Clock Table and Nomenclature (60-MHz Devices)
        4. Table 5-10 Device Clocking Requirements/Characteristics
        5. Table 5-11 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-12 XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-13 XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-14 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-15 Flash/OTP Endurance for T Temperature Material
      2. Table 5-16 Flash/OTP Endurance for S Temperature Material
      3. Table 5-17 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-18 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-19 Flash Parameters at 50-MHz SYSCLKOUT
      6. Table 5-20 Flash Parameters at 40-MHz SYSCLKOUT
      7. Table 5-21 Flash Program/Erase Time
      8. Table 5-22 Flash/OTP Access Timing
      9. Table 5-23 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  Flash
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0 SARAM
      8. 6.1.8  Boot ROM
        1. 6.1.8.1 Emulation Boot
        2. 6.1.8.2 GetMode
        3. 6.1.8.3 Peripheral Pins Used by the Bootloader
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1–XINT3)
      12. 6.1.12 Internal Zero Pin Oscillators, Oscillator, and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG/BOR/POR
      1. 6.5.1 On-chip Voltage Regulator (VREG)
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 6.6.5 CPU Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-21 External Interrupt Timing Requirements
          2. Table 6-22 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Analog Block
        1. 6.9.1.1 Analog-to-Digital Converter (ADC)
          1. 6.9.1.1.1 Features
          2. 6.9.1.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-25 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.1.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-26  ADC Electrical Characteristics
            2. Table 6-27  ADC Power Modes
            3. 6.9.1.1.3.1 Internal Temperature Sensor
              1. Table 6-28 Temperature Sensor Coefficient
            4. 6.9.1.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-29 ADC Power-Up Delays
            5. 6.9.1.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.1.2 ADC MUX
        3. 6.9.1.3 Comparator Block
          1. 6.9.1.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-31 Electrical Characteristics of the Comparator/DAC
      2. 6.9.2  Detailed Descriptions
      3. 6.9.3  Serial Peripheral Interface (SPI) Module
        1. 6.9.3.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-33 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-34 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.3.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-35 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-36 SPI Slave Mode External Timing (Clock Phase = 1)
      4. 6.9.4  Serial Communications Interface (SCI) Module
      5. 6.9.5  Inter-Integrated Circuit (I2C)
        1. 6.9.5.1 I2C Electrical Data/Timing
          1. Table 6-39 I2C Timing Requirements
          2. Table 6-40 I2C Switching Characteristics
      6. 6.9.6  Enhanced PWM Modules (ePWM1/2/3/4)
        1. 6.9.6.1 ePWM Electrical Data/Timing
          1. Table 6-42 ePWM Timing Requirements
          2. Table 6-43 ePWM Switching Characteristics
        2. 6.9.6.2 Trip-Zone Input Timing
          1. Table 6-44 Trip-Zone Input Timing Requirements
      7. 6.9.7  High-Resolution PWM (HRPWM)
        1. 6.9.7.1 HRPWM Electrical Data/Timing
          1. Table 6-45 High-Resolution PWM Characteristics at SYSCLKOUT = 50 MHz–60 MHz
      8. 6.9.8  Enhanced Capture Module (eCAP1)
        1. 6.9.8.1 eCAP Electrical Data/Timing
          1. Table 6-47 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-48 eCAP Switching Characteristics
      9. 6.9.9  JTAG Port
      10. 6.9.10 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.10.1 GPIO Electrical Data/Timing
          1. 6.9.10.1.1 GPIO - Output Timing
            1. Table 6-54 General-Purpose Output Switching Characteristics
          2. 6.9.10.1.2 GPIO - Input Timing
            1. Table 6-55 General-Purpose Input Timing Requirements
          3. 6.9.10.1.3 Sampling Window Width for Input Signals
          4. 6.9.10.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-56 IDLE Mode Timing Requirements
            2. Table 6-57 IDLE Mode Switching Characteristics
            3. Table 6-58 STANDBY Mode Timing Requirements
            4. Table 6-59 STANDBY Mode Switching Characteristics
            5. Table 6-60 HALT Mode Timing Requirements
            6. Table 6-61 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

System Control

This section describes the oscillator and clocking mechanisms, the watchdog function and the low-power modes.

Table 6-12 PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME ADDRESS SIZE (x16) DESCRIPTION(1)
BORCFG 0x00 0985 1 BOR Configuration Register
XCLK 0x00 7010 1 XCLKOUT Control
PLLSTS 0x00 7011 1 PLL Status Register
CLKCTL 0x00 7012 1 Clock Control Register
PLLLOCKPRD 0x00 7013 1 PLL Lock Period
INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register
INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register
LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register
PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0
PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1
LPMCR0 0x00 701E 1 Low-Power Mode Control Register 0
PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3
PLLCR 0x00 7021 1 PLL Control Register
SCSR 0x00 7022 1 System Control and Status Register
WDCNTR 0x00 7023 1 Watchdog Counter Register
WDKEY 0x00 7025 1 Watchdog Reset Key Register
WDCR 0x00 7029 1 Watchdog Control Register
All registers in this table are EALLOW protected.

Figure 6-7 shows the various clock domains that are discussed. Figure 6-8 shows the various clock sources (both internal and external) that can provide a clock for device operation.

TMS320F28027 TMS320F28027F TMS320F28026 TMS320F28026F TMS320F28023 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200 sys_dia_sprs523.gif
CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT).
Figure 6-7 Clock and Reset Domains
TMS320F28027 TMS320F28027F TMS320F28026 TMS320F28026F TMS320F28023 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200 schem_prs523.gif
Register loaded from TI OTP-based calibration function.
See Section 6.6.4 for details on missing clock detection.
Figure 6-8 Clock Tree