The CPU watchdog module on the 2803x device is similar to the one used on the 281x/280x/283xx devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter. Figure 6-11 shows the various functional blocks within the watchdog module.
Normally, when the input clocks are present, the CPU watchdog counter decrements to initiate a CPU watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU watchdog counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock).
The CPU watchdog is different from the NMI watchdog. It is the legacy watchdog that is present in all 28x devices.
Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory.
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the CPU watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 6.7, Low-power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of IDLE mode.
In HALT mode, the CPU watchdog can be used to wake up the device through a device reset.