SPRS584N April   2009  – June 2020 TMS320F28030 , TMS320F28031 , TMS320F28032 , TMS320F28033 , TMS320F28034 , TMS320F28035

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT
      2. 5.5.1     Reducing Current Consumption
      3. 5.5.2     Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PN Package
      2. 5.7.2 PAG Package
      3. 5.7.3 RSH Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-5 2803x Clock Table and Nomenclature (60-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-8  XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-9  XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator (CLA)
      3. 6.1.3  Memory Bus (Harvard Bus Architecture)
      4. 6.1.4  Peripheral Bus
      5. 6.1.5  Real-Time JTAG and Analysis
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Emulation Boot
        2. 6.1.9.2 GetMode
        3. 6.1.9.3 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1–XINT3)
      13. 6.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG/BOR/POR
      1. 6.5.1 On-chip Voltage Regulator (VREG)
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 6.6.5 CPU Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-22 External Interrupt Timing Requirements
          2. Table 6-23 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Control Law Accelerator (CLA) Overview
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter (ADC)
          1. 6.9.2.1.1 Features
          2. 6.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-28 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-29  ADC Electrical Characteristics
            2. Table 6-30  ADC Power Modes
            3. 6.9.2.1.3.1 Internal Temperature Sensor
              1. Table 6-31 Temperature Sensor Coefficient
            4. 6.9.2.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-32 ADC Power-Up Delays
            5. 6.9.2.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 ADC MUX
        3. 6.9.2.3 Comparator Block
          1. 6.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-34 Electrical Characteristics of the Comparator/DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface (SPI) Module
        1. 6.9.4.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-37 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-38 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-39 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-40 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface (SCI) Module
      6. 6.9.6  Local Interconnect Network (LIN)
      7. 6.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 6.9.8  Inter-Integrated Circuit (I2C)
        1. 6.9.8.1 I2C Electrical Data/Timing
          1. Table 6-46 I2C Timing Requirements
          2. Table 6-47 I2C Switching Characteristics
      9. 6.9.9  Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)
        1. 6.9.9.1 ePWM Electrical Data/Timing
          1. Table 6-50 ePWM Timing Requirements
          2. Table 6-51 ePWM Switching Characteristics
        2. 6.9.9.2 Trip-Zone Input Timing
          1. Table 6-52 Trip-Zone Input Timing Requirements
      10. 6.9.10 High-Resolution PWM (HRPWM)
        1. 6.9.10.1 HRPWM Electrical Data/Timing
          1. Table 6-53 High-Resolution PWM Characteristics
      11. 6.9.11 Enhanced Capture Module (eCAP1)
        1. 6.9.11.1 eCAP Electrical Data/Timing
          1. Table 6-55 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-56 eCAP Switching Characteristics
      12. 6.9.12 High-Resolution Capture (HRCAP) Module
        1. 6.9.12.1 HRCAP Electrical Data/Timing
          1. Table 6-58 High-Resolution Capture (HRCAP) Timing Requirements
      13. 6.9.13 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.9.13.1 eQEP Electrical Data/Timing
          1. Table 6-60 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. Table 6-61 eQEP Switching Characteristics
      14. 6.9.14 JTAG Port
      15. 6.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.15.1 GPIO Electrical Data/Timing
          1. 6.9.15.1.1 GPIO - Output Timing
            1. Table 6-67 General-Purpose Output Switching Characteristics
          2. 6.9.15.1.2 GPIO - Input Timing
            1. Table 6-68 General-Purpose Input Timing Requirements
          3. 6.9.15.1.3 Sampling Window Width for Input Signals
          4. 6.9.15.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-69 IDLE Mode Timing Requirements
            2. Table 6-70 IDLE Mode Switching Characteristics
            3. Table 6-71 STANDBY Mode Timing Requirements
            4. Table 6-72 STANDBY Mode Switching Characteristics
            5. Table 6-73 HALT Mode Timing Requirements
            6. Table 6-74 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

High-Resolution Capture (HRCAP) Module

The High-Resolution Capture (HRCAP) module measures the difference between external pulses with a typical resolution of 300 ps.

Uses for the HRCAP include:

  • Capactive touch applications
  • High-resolution period and duty cycle measurements of pulse train cycles
  • Instantaneous speed measurements
  • Instantaneous frequency measurements
  • Voltage measurements across an isolation boundary
  • Distance/sonar measurement and scanning

The HRCAP module features include:

  • Pulse width capture in either non-high-resolution or high-resolution modes
  • Difference (Delta) mode pulse width capture
  • Typical high-resolution capture on the order of 300 ps resolution on each edge
  • Interrupt on either falling or rising edge
  • Continuous mode capture of pulse widths in 2-deep buffer
  • Calibration logic for precision high-resolution capture
  • All of the above resources are dedicated to a single input pin
  • HRCAP calibration software library supplied by TI is used for both calibration and calculating fractional pulse widths

The HRCAP module includes one capture channel in addition to a high-resolution calibration block, which connects internally to the last available ePWMxA HRPWM channel when calibrating (that is, if there are eight ePWMs with HRPWM capability, it will be HRPWM8A).

Each HRCAP channel has the following independent key resources:

  • Dedicated input capture pin
  • 16-bit HRCAP clock which is either equal to the PLL output frequency (asynchronous to SYSCLK) or equal to the SYSCLK frequency (synchronous to SYSCLK)
  • High-resolution pulse width capture in a 2-deep buffer

TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 fbd_hrcap_prs584.gifFigure 6-42 HRCAP Functional Block Diagram

Table 6-57 HRCAP Registers

NAME HRCAP1 HRCAP2 SIZE (x16) DESCRIPTION
HCCTL 0x6AC0 0x6AE0 1 HRCAP Control Register(1)
HCIFR 0x6AC1 0x6AE1 1 HRCAP Interrupt Flag Register
HCICLR 0x6AC2 0x6AE2 1 HRCAP Interrupt Clear Register
HCIFRC 0x6AC3 0x6AE3 1 HRCAP Interrupt Force Register
HCCOUNTER 0x6AC4 0x6AE4 1 HRCAP 16-bit Counter Register
HCCAPCNTRISE0 0x6AD0 0x6AF0 1 HRCAP Capture Counter on Rising Edge 0 Register
HCCAPCNTFALL0 0x6AD2 0x6AF2 1 HRCAP Capture Counter on Falling Edge 0 Register
HCCAPCNTRISE1 0x6AD8 0x6AF8 1 HRCAP Capture Counter on Rising Edge 1 Register
HCCAPCNTFALL1 0x6ADA 0x6AFA 1 HRCAP Capture Counter on Falling Edge 1 Register
Registers that are EALLOW-protected.

For more information on the HRCAP, see the High Resolution Capture (HRCAP) chapter in the TMS320F2803x Technical Reference Manual.