SPRS797C November   2012  – October 2018 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28053 , TMS320F28054 , TMS320F28055

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Power Consumption Summary
      1. Table 5-1 TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
      2. 5.4.1     Reducing Current Consumption
      3. 5.4.2     Current Consumption Graphs (VREG Enabled)
    5. 5.5  Electrical Characteristics
    6. 5.6  Thermal Resistance Characteristics for PN Package
    7. 5.7  Thermal Design Considerations
    8. 5.8  Emulator Connection Without Signal Buffering for the MCU
    9. 5.9  Parameter Information
      1. 5.9.1 Timing Parameter Symbology
      2. 5.9.2 General Notes on Timing Parameters
    10. 5.10 Test Load Circuit
    11. 5.11 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    12. 5.12 Clock Specifications
      1. 5.12.1 Device Clock Table
        1. Table 5-5 2805x Clock Table and Nomenclature (60-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
      2. 5.12.2 Clock Requirements and Characteristics
        1. Table 5-8  XCLKIN Timing Requirements - PLL Enabled
        2. Table 5-9  XCLKIN Timing Requirements - PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    13. 5.13 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator
      3. 6.1.3  Memory Bus (Harvard Bus Architecture)
      4. 6.1.4  Peripheral Bus
      5. 6.1.5  Real-Time JTAG and Analysis
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Emulation Boot
        2. 6.1.9.2 GetMode
        3. 6.1.9.3 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion Block
      12. 6.1.12 External Interrupts (XINT1 to XINT3)
      13. 6.1.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Map
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG, BOR, POR
      1. 6.5.1 On-chip VREG
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset and Brownout Reset Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero-Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI-watchdog Function)
      5. 6.6.5 CPU-watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-26 External Interrupt Timing Requirements
          2. Table 6-27 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Control Law Accelerator
        1. 6.9.1.1 CLA Device-Specific Information
        2. 6.9.1.2 CLA Register Descriptions
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter
          1. 6.9.2.1.1 ADC Device-Specific Information
          2. 6.9.2.1.2 ADC Electrical Data/Timing
            1. Table 6-32  ADC Electrical Characteristics
            2. Table 6-34  ADC Power Modes
            3. 6.9.2.1.2.1 External ADC Start-of-Conversion Electrical Data/Timing
              1. Table 6-35 External ADC Start-of-Conversion Switching Characteristics
            4. 6.9.2.1.2.2 Internal Temperature Sensor
              1. Table 6-36 Temperature Sensor Coefficient
            5. 6.9.2.1.2.3 ADC Power-Up Control Bit Timing
              1. Table 6-37 ADC Power-Up Delays
            6. 6.9.2.1.2.4 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 Analog Front End
          1. 6.9.2.2.1 AFE Device-Specific Information
          2. 6.9.2.2.2 AFE Register Descriptions
          3. 6.9.2.2.3 PGA Electrical Data/Timing
          4. 6.9.2.2.4 Comparator Block Electrical Data/Timing
            1. Table 6-45 Electrical Characteristics of the Comparator/DAC
          5. 6.9.2.2.5 VREFOUT Buffered DAC Electrical Data
            1. Table 6-46 Electrical Characteristics of VREFOUT Buffered DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface
        1. 6.9.4.1 SPI Device-Specific Information
        2. 6.9.4.2 SPI Register Descriptions
        3. 6.9.4.3 SPI Master Mode Electrical Data/Timing
          1. Table 6-48 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-49 SPI Master Mode External Timing (Clock Phase = 1)
        4. 6.9.4.4 SPI Slave Mode Electrical Data/Timing
          1. Table 6-50 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-51 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface
        1. 6.9.5.1 SCI Device-Specific Information
        2. 6.9.5.2 SCI Register Descriptions
      6. 6.9.6  Enhanced Controller Area Network
        1. 6.9.6.1 eCAN Device-Specific Information
        2. 6.9.6.2 eCAN Register Descriptions
      7. 6.9.7  Inter-Integrated Circuit
        1. 6.9.7.1 I2C Device-Specific Information
        2. 6.9.7.2 I2C Register Descriptions
        3. 6.9.7.3 I2C Electrical Data/Timing
          1. Table 6-58 I2C Timing Requirements
          2. Table 6-59 I2C Switching Characteristics
      8. 6.9.8  Enhanced Pulse Width Modulator
        1. 6.9.8.1 ePWM Device-Specific Information
        2. 6.9.8.2 ePWM Register Descriptions
        3. 6.9.8.3 ePWM Electrical Data/Timing
          1. Table 6-62 ePWM Timing Requirements
          2. Table 6-63 ePWM Switching Characteristics
          3. 6.9.8.3.1  Trip-Zone Input Timing
            1. Table 6-64 Trip-Zone Input Timing Requirements
      9. 6.9.9  Enhanced Capture Module
        1. 6.9.9.1 eCAP Module Device-Specific Information
        2. 6.9.9.2 eCAP Module Register Descriptions
        3. 6.9.9.3 eCAP Module Electrical Data/Timing
          1. Table 6-66 eCAP Timing Requirement
          2. Table 6-67 eCAP Switching Characteristics
      10. 6.9.10 Enhanced Quadrature Encoder Pulse
        1. 6.9.10.1 eQEP Device-Specific Information
        2. 6.9.10.2 eQEP Register Descriptions
        3. 6.9.10.3 eQEP Electrical Data/Timing
          1. Table 6-69 eQEP Timing Requirements
          2. Table 6-70 eQEP Switching Characteristics
      11. 6.9.11 JTAG Port
        1. 6.9.11.1 JTAG Port Device-Specific Information
      12. 6.9.12 General-Purpose Input/Output
        1. 6.9.12.1 GPIO Device-Specific Information
        2. 6.9.12.2 GPIO Register Descriptions
        3. 6.9.12.3 GPIO Electrical Data/Timing
          1. 6.9.12.3.1 GPIO - Output Timing
            1. Table 6-74 General-Purpose Output Switching Characteristics
          2. 6.9.12.3.2 GPIO - Input Timing
            1. Table 6-75 General-Purpose Input Timing Requirements
          3. 6.9.12.3.3 Sampling Window Width for Input Signals
          4. 6.9.12.3.4 Low-Power Mode Wakeup Timing
            1. Table 6-76 IDLE Mode Timing Requirements
            2. Table 6-77 IDLE Mode Switching Characteristics
            3. Table 6-78 STANDBY Mode Timing Requirements
            4. Table 6-79 STANDBY Mode Switching Characteristics
            5. Table 6-80 HALT Mode Timing Requirements
            6. Table 6-81 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 6-81 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low 32tc(SCO) 45tc(SCO) cycles
tp PLL lock-up time 1 ms
td(WAKE-HALT) Delay time, PLL lock to program execution resume
  • Wake up from flash
    • Flash module in sleep state
1125tc(SCO) cycles
  • Wake up from SARAM
35tc(SCO) cycles
TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051 TMS320F28050 td_halt_wk_prs584.gif
IDLE instruction is executed to put the device into HALT mode.
The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated as follows before oscillator is turned off and the CLKIN to the core is stopped:
  • 16 cycles, when DIVSEL = 00 or 01
  • 32 cycles, when DIVSEL = 10
  • 64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT mode. Keeping INTOSC1, INTOSC2, and the watchdog alive in HALT mode is done by writing to the appropriate bits in the CLKCTL register. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized, which enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited.
Normal operation resumes.
From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-50 HALT Wake-Up Using GPIOn