SPRS797D November   2012  – June 2020 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052F , TMS320F28052M , TMS320F28053 , TMS320F28054 , TMS320F28054F , TMS320F28054M , TMS320F28055

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
      2. 5.5.1     Reducing Current Consumption
      3. 5.5.2     Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics for PN Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-5 2805x Clock Table and Nomenclature (60-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-8  XCLKIN Timing Requirements - PLL Enabled
        2. Table 5-9  XCLKIN Timing Requirements - PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator
      3. 6.1.3  Memory Bus (Harvard Bus Architecture)
      4. 6.1.4  Peripheral Bus
      5. 6.1.5  Real-Time JTAG and Analysis
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Emulation Boot
        2. 6.1.9.2 GetMode
        3. 6.1.9.3 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion Block
      12. 6.1.12 External Interrupts (XINT1 to XINT3)
      13. 6.1.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Map
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG, BOR, POR
      1. 6.5.1 On-chip VREG
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset and Brownout Reset Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero-Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI-watchdog Function)
      5. 6.6.5 CPU-watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-26 External Interrupt Timing Requirements
          2. Table 6-27 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Control Law Accelerator
        1. 6.9.1.1 CLA Device-Specific Information
        2. 6.9.1.2 CLA Register Descriptions
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter
          1. 6.9.2.1.1 ADC Device-Specific Information
          2. 6.9.2.1.2 ADC Electrical Data/Timing
            1. Table 6-32  ADC Electrical Characteristics
            2. Table 6-34  ADC Power Modes
            3. 6.9.2.1.2.1 External ADC Start-of-Conversion Electrical Data/Timing
              1. Table 6-35 External ADC Start-of-Conversion Switching Characteristics
            4. 6.9.2.1.2.2 Internal Temperature Sensor
              1. Table 6-36 Temperature Sensor Coefficient
            5. 6.9.2.1.2.3 ADC Power-Up Control Bit Timing
              1. Table 6-37 ADC Power-Up Delays
            6. 6.9.2.1.2.4 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 Analog Front End
          1. 6.9.2.2.1 AFE Device-Specific Information
          2. 6.9.2.2.2 AFE Register Descriptions
          3. 6.9.2.2.3 PGA Electrical Data/Timing
          4. 6.9.2.2.4 Comparator Block Electrical Data/Timing
            1. Table 6-45 Electrical Characteristics of the Comparator/DAC
          5. 6.9.2.2.5 VREFOUT Buffered DAC Electrical Data
            1. Table 6-46 Electrical Characteristics of VREFOUT Buffered DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface
        1. 6.9.4.1 SPI Device-Specific Information
        2. 6.9.4.2 SPI Register Descriptions
        3. 6.9.4.3 SPI Master Mode Electrical Data/Timing
          1. Table 6-48 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-49 SPI Master Mode External Timing (Clock Phase = 1)
        4. 6.9.4.4 SPI Slave Mode Electrical Data/Timing
          1. Table 6-50 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-51 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface
        1. 6.9.5.1 SCI Device-Specific Information
        2. 6.9.5.2 SCI Register Descriptions
      6. 6.9.6  Enhanced Controller Area Network
        1. 6.9.6.1 eCAN Device-Specific Information
        2. 6.9.6.2 eCAN Register Descriptions
      7. 6.9.7  Inter-Integrated Circuit
        1. 6.9.7.1 I2C Device-Specific Information
        2. 6.9.7.2 I2C Register Descriptions
        3. 6.9.7.3 I2C Electrical Data/Timing
          1. Table 6-58 I2C Timing Requirements
          2. Table 6-59 I2C Switching Characteristics
      8. 6.9.8  Enhanced Pulse Width Modulator
        1. 6.9.8.1 ePWM Device-Specific Information
        2. 6.9.8.2 ePWM Register Descriptions
        3. 6.9.8.3 ePWM Electrical Data/Timing
          1. Table 6-62 ePWM Timing Requirements
          2. Table 6-63 ePWM Switching Characteristics
          3. 6.9.8.3.1  Trip-Zone Input Timing
            1. Table 6-64 Trip-Zone Input Timing Requirements
      9. 6.9.9  Enhanced Capture Module
        1. 6.9.9.1 eCAP Module Device-Specific Information
        2. 6.9.9.2 eCAP Module Register Descriptions
        3. 6.9.9.3 eCAP Module Electrical Data/Timing
          1. Table 6-66 eCAP Timing Requirement
          2. Table 6-67 eCAP Switching Characteristics
      10. 6.9.10 Enhanced Quadrature Encoder Pulse
        1. 6.9.10.1 eQEP Device-Specific Information
        2. 6.9.10.2 eQEP Register Descriptions
        3. 6.9.10.3 eQEP Electrical Data/Timing
          1. Table 6-69 eQEP Timing Requirements
          2. Table 6-70 eQEP Switching Characteristics
      11. 6.9.11 JTAG Port
        1. 6.9.11.1 JTAG Port Device-Specific Information
      12. 6.9.12 General-Purpose Input/Output
        1. 6.9.12.1 GPIO Device-Specific Information
        2. 6.9.12.2 GPIO Register Descriptions
        3. 6.9.12.3 GPIO Electrical Data/Timing
          1. 6.9.12.3.1 GPIO - Output Timing
            1. Table 6-74 General-Purpose Output Switching Characteristics
          2. 6.9.12.3.2 GPIO - Input Timing
            1. Table 6-75 General-Purpose Input Timing Requirements
          3. 6.9.12.3.3 Sampling Window Width for Input Signals
          4. 6.9.12.3.4 Low-Power Mode Wakeup Timing
            1. Table 6-76 IDLE Mode Timing Requirements
            2. Table 6-77 IDLE Mode Switching Characteristics
            3. Table 6-78 STANDBY Mode Timing Requirements
            4. Table 6-79 STANDBY Mode Switching Characteristics
            5. Table 6-80 HALT Mode Timing Requirements
            6. Table 6-81 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Support Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1.10 Security

The TMS320F2805x device supports high levels of security with a dual-zone (Z1/Z2) feature to protect user's firmware from being reverse-engineered. The dual-zone feature enables the user to co-develop application software with a third-party or subcontractor by preventing visibility into each other's software IP. The security features a 128-bit password (hardcoded for 16 wait states) for each zone, which the user programs into the USER-OTP. Each zone has its own dedicated USER-OTP, which must be programmed by the user with the required security settings, including the 128-bit password. Because OTP cannot be erased, to provide the user with the flexibility of changing security-related settings and passwords multiple times, a 32-bit link pointer is stored at the beginning of each USER-OTP. Because the user can only flip a 1 in USER-OTP to 0, the most significant bit position in the link pointer, programmed as 0, defines the USER-OTP region (zone-select) for each zone in which security-related settings and passwords are stored. Table 6-3 provides the location of the zone-select block based on the link pointer. Table 6-4 shows the zone-select block organization in USER-OTP.

Table 6-3 Location of Zone-Select Block Based on Link Pointer

Zx LINK POINTER VALUE ADDRESS OFFSET FOR ZONE-SELECT
32’bxx111111111111111111111111111111 0x10
32’bxx111111111111111111111111111110 0x20
32’bxx11111111111111111111111111110x 0x30
32’bxx1111111111111111111111111110xx 0x40
32’bxx111111111111111111111111110xxx 0x50
32’bxx11111111111111111111111110xxxx 0x60
32’bxx1111111111111111111111110xxxxx 0x70
32’bxx111111111111111111111110xxxxxx 0x80
32’bxx11111111111111111111110xxxxxxx 0x90
32’bxx1111111111111111111110xxxxxxxx 0xa0
32’bxx111111111111111111110xxxxxxxxx 0xb0
32’bxx11111111111111111110xxxxxxxxxx 0xc0
32’bxx1111111111111111110xxxxxxxxxxx 0xd0
32’bxx111111111111111110xxxxxxxxxxxx 0xe0
32’bxx11111111111111110xxxxxxxxxxxxx 0xf0
32’bxx1111111111111110xxxxxxxxxxxxxx 0x100
32’bxx111111111111110xxxxxxxxxxxxxxx 0x110
32’bxx11111111111110xxxxxxxxxxxxxxxx 0x120
32’bxx1111111111110xxxxxxxxxxxxxxxxx 0x130
32’bxx111111111110xxxxxxxxxxxxxxxxxx 0x140
32’bxx11111111110xxxxxxxxxxxxxxxxxxx 0x150
32’bxx1111111110xxxxxxxxxxxxxxxxxxxx 0x160
32’bxx111111110xxxxxxxxxxxxxxxxxxxxx 0x170
32’bxx11111110xxxxxxxxxxxxxxxxxxxxxx 0x180
32’bxx1111110xxxxxxxxxxxxxxxxxxxxxxx 0x190
32’bxx111110xxxxxxxxxxxxxxxxxxxxxxxx 0x1a0
32’bxx11110xxxxxxxxxxxxxxxxxxxxxxxxx 0x1b0
32’bxx1110xxxxxxxxxxxxxxxxxxxxxxxxxx 0x1c0
32’bxx110xxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1d0
32’bxx10xxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1e0
32’bxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1f0

Table 6-4 Zone-Select Block Organization in USER-OTP

16-BIT ADDRESS OFFSET
(WITH RESPECT TO OFFSET OF ZONE-SELECT)		 CONTENT
0x0 Zx-EXEONLYRAM
0x1
0x2 Zx-EXEONLYSECT
0x3
0x4 Zx-GRABRAM
0x5
0x6 Zx-GRABSECT
0x7
0x8 Zx-CSMPSWD0
0x9
0xa Zx-CSMPSWD1
0xb
0xc Zx-CSMPSWD2
0xd
0xe Zx-CSMPSWD3
0xf

The Dual Code Security Module (DCSM) is used to protect the flash/OTP/Lx SARAM blocks/CLA/Secure ROM content. Individual flash sectors and SARAM blocks can be attached to any of the secure zone at start-up time. Secure ROM and the CLA are always attached to Z1. Resources attached to (owned by) one zone do not have any access to code running in the other zone when it is secured. Individual flash sectors, as well as SARAM blocks, can be further protected by enabling the EXEONLY protection. EXEONLY flash sectors or SARAM blocks do not have READ/WRITE access. Only code execution is allowed from such memory blocks.

The security feature prevents unauthorized users from examining memory contents through the JTAG port, executing code from external memory, or trying to boot load an undesirable software that would export the secure memory contents. To enable access to the secure blocks of a particular zone, the user must write a 128-bit value in the CSMKEY registers of the zone; this value must match the values stored in the password locations in USER-OTP. If the 128 bits of the password locations in USER-OTP of a particular zone are all 1s (unprogrammed), then the security for that zone gets UNLOCKED as soon as a dummy read is done to the password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case).

In addition to the DCSM, the Emulation Code Security Logic (ECSL) has been implemented for each zone to prevent unauthorized users from stepping through secure code. A halt inside secure code will trip the ECSL and break the emulation connection. To allow emulation of secure code while maintaining DCSM protection against secure memory reads, the user must write the lower 64 bits of the USER-OTP password into the CSMKEY register of the zone to disable the ECSL. Dummy reads of all 128 bits of the password for that particular zone in USER-OTP must still be performed. If the lower 64 bits of the password locations of a particular zone are all zeros, then the ECSL for that zone gets disabled as soon as a dummy read is done to the password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case).

When initially debugging a device with the password locations in OTP (that is, secured), the CPU will start running and may execute an instruction that performs an access to ECSL-protected area. If the CPU execution is halted when the program counter belongs to the secure code region, the ECSL will trip and cause the JTAG debug probe connection to be cut. The solution is to use the Wait boot option. The Wait boot option will sit in a loop around a software breakpoint to allow a JTAG debug probe to be connected without tripping security. The user can then exit this mode once the JTAG debug probe is connected by using one of the emulation boot options as described in the Boot ROM chapter of the TMS320x2805x Technical Reference Manual. The 2805x devices do not support hardware wait-in-reset mode.

To prevent reverse-engineering of the code in secure zone, unauthorized users are prevented from looking at the CPU registers in the CCS Expressions Window. The values in the Expressions Window for all of these registers, except for PC and some status bits, display false values when code is running from a secure zone. This feature gets disabled if the zone is unlocked.

NOTE

  • The USER-OTP contains security-related settings for their respective zone. Execution is not allowed from the USER-OTP; therefore, the user should not keep any code/data in this region.
  • The 128-bit password must not be programmed to zeros. Doing so would permanently lock the device.
  • The user must try not to write into the CPU registers through the debugger watch window when code is running/halted from/inside secure zone. This may corrupt the execution of the actual program.

DISCLAIMER

Dual Code Security Module Disclaimer

THE DUAL CODE SECURITY MODULE (DCSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE DCSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE DCSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE DCSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.