SPRS698H November 2010 – March 2020 TMS320F28062 , TMS320F28062F , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069F , TMS320F28069M
The devices support the following peripherals that are used for embedded control and communication:
|ePWM:||The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the HRPWM high-resolution duty and period features. The type 1 module found on 2806x devices also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced triggering including trip functions based on comparator outputs.|
|eCAP:||The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
|eQEP:||The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals.|
|ADC:||The ADC block is a 12-bit converter. The ADC has up to 16 single-ended channels pinned out, depending on the device. The ADC also contains two sample-and-hold units for simultaneous sampling.|
|Comparator:||Each comparator block consists of one analog comparator along with an internal 10-bit reference for supplying one input of the comparator.|
|HRCAP:||The high-resolution capture peripheral operates in normal capture mode through a 16-bit counter clocked off of the HCCAPCLK or in high-resolution capture mode by using built-in calibration logic in conjunction with a TI-supplied calibration library.|