SPRS698H November   2010  – March 2020 TMS320F28062 , TMS320F28062F , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069F , TMS320F28069M

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
    5. 1.5 System Device Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT
      2. 5.5.1     Reducing Current Consumption
      3. 5.5.2     Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PFP PowerPAD Package
      2. 5.7.2 PZP PowerPAD Package
      3. 5.7.3 PN Package
      4. 5.7.4 PZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Debug Probe Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-5 2806x Clock Table and Nomenclature (90-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-8  XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-9  XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 90-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator (CLA)
      3. 6.1.3  Viterbi, Complex Math, CRC Unit (VCU)
      4. 6.1.4  Memory Bus (Harvard Bus Architecture)
      5. 6.1.5  Peripheral Bus
      6. 6.1.6  Real-Time JTAG and Analysis
      7. 6.1.7  Flash
      8. 6.1.8  M0, M1 SARAMs
      9. 6.1.9  L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs
      10. 6.1.10 Boot ROM
        1. 6.1.10.1 Emulation Boot
        2. 6.1.10.2 GetMode
        3. 6.1.10.3 Peripheral Pins Used by the Bootloader
      11. 6.1.11 Security
      12. 6.1.12 Peripheral Interrupt Expansion (PIE) Block
      13. 6.1.13 External Interrupts (XINT1 to XINT3)
      14. 6.1.14 Internal Zero Pin Oscillators, Oscillator, and PLL
      15. 6.1.15 Watchdog
      16. 6.1.16 Peripheral Clocking
      17. 6.1.17 Low-power Modes
      18. 6.1.18 Peripheral Frames 0, 1, 2, 3 (PFn)
      19. 6.1.19 General-Purpose Input/Output (GPIO) Multiplexer
      20. 6.1.20 32-Bit CPU-Timers (0, 1, 2)
      21. 6.1.21 Control Peripherals
      22. 6.1.22 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG, BOR, POR
      1. 6.5.1 On-chip VREG
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brownout Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 USB and HRCAP PLL Module (PLL2)
      5. 6.6.5 Loss of Input Clock (NMI Watchdog Function)
      6. 6.6.6 CPU Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-20 External Interrupt Timing Requirements
          2. Table 6-21 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  CLA Overview
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter (ADC)
          1. 6.9.2.1.1 Features
          2. 6.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-26 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-27  ADC Electrical Characteristics
            2. Table 6-28  ADC Power Modes
            3. 6.9.2.1.3.1 Internal Temperature Sensor
              1. Table 6-29 Temperature Sensor Coefficient
            4. 6.9.2.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-30 ADC Power-Up Delays
            5. 6.9.2.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 ADC MUX
        3. 6.9.2.3 Comparator Block
          1. 6.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-32 Electrical Characteristics of the Comparator/DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface (SPI) Module
        1. 6.9.4.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-35 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-36 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-37 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-38 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface (SCI) Module
      6. 6.9.6  Multichannel Buffered Serial Port (McBSP) Module
        1. 6.9.6.1 McBSP Electrical Data/Timing
          1. 6.9.6.1.1 McBSP Transmit and Receive Timing
            1. Table 6-42 McBSP Timing Requirements
            2. Table 6-43 McBSP Switching Characteristics
          2. 6.9.6.1.2 McBSP as SPI Master or Slave Timing
            1. Table 6-44 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 6-45 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 6-46 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 6-47 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 6-48 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 6-49 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 6-50 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 6-51 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      7. 6.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 6.9.8  Inter-Integrated Circuit (I2C)
        1. 6.9.8.1 I2C Electrical Data/Timing
          1. Table 6-55 I2C Timing Requirements
          2. Table 6-56 I2C Switching Characteristics
      9. 6.9.9  Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)
        1. 6.9.9.1 ePWM Electrical Data/Timing
          1. Table 6-59 ePWM Timing Requirements
          2. Table 6-60 ePWM Switching Characteristics
        2. 6.9.9.2 Trip-Zone Input Timing
          1. Table 6-61 Trip-Zone Input Timing Requirements
      10. 6.9.10 High-Resolution PWM (HRPWM)
        1. 6.9.10.1 HRPWM Electrical Data/Timing
          1. Table 6-62 High-Resolution PWM Characteristics
      11. 6.9.11 Enhanced Capture Module (eCAP1)
        1. 6.9.11.1 eCAP Electrical Data/Timing
          1. Table 6-64 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-65 eCAP Switching Characteristics
      12. 6.9.12 High-Resolution Capture Modules (HRCAP1 to HRCAP4)
        1. 6.9.12.1 HRCAP Electrical Data/Timing
          1. Table 6-67 High-Resolution Capture (HRCAP) Timing Requirements
      13. 6.9.13 Enhanced Quadrature Encoder Modules (eQEP1, eQEP2)
        1. 6.9.13.1 eQEP Electrical Data/Timing
          1. Table 6-69 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. Table 6-70 eQEP Switching Characteristics
      14. 6.9.14 JTAG Port
      15. 6.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.15.1 GPIO Electrical Data/Timing
          1. 6.9.15.1.1 GPIO Output Timing
            1. Table 6-76 General-Purpose Output Switching Characteristics
          2. 6.9.15.1.2 GPIO Input Timing
            1. Table 6-77 General-Purpose Input Timing Requirements
          3. 6.9.15.1.3 Sampling Window Width for Input Signals
          4. 6.9.15.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-78 IDLE Mode Timing Requirements
            2. Table 6-79 IDLE Mode Switching Characteristics
            3. Table 6-80 STANDBY Mode Timing Requirements
            4. Table 6-81 STANDBY Mode Switching Characteristics
            5. Table 6-82 HALT Mode Timing Requirements
            6. Table 6-83 HALT Mode Switching Characteristics
      16. 6.9.16 Universal Serial Bus (USB)
        1. 6.9.16.1 USB Electrical Data/Timing
          1. Table 6-84 USB Input Ports DP and DM Timing Requirements
          2. Table 6-85 USB Output Ports DP and DM Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Device Comparison

Table 3-1 lists the features of the TMS320F2806x devices.

Table 3-1 Device Comparison

FEATURE TYPE(1) 28069
28069U(2)(5)
28069M(2)(3)
28069F(2)(3)
(90 MHz)		 28068U(2)(5)
28068M(2)(3)
28068F(2)(3)
(90 MHz)		 28067
28067U(2)(5)
(90 MHz)		 28066
28066U(2)(5)
(90 MHz)		 28065
28065U(2)(5)
(90 MHz)		 28064
28064U(2)(5)
(90 MHz)		 28063
28063U(2)(5)
(90 MHz)		 28062
28062U(2)(5)
28062F(2)(3)
(90 MHz)
Package Type
(PFP and PZP are PowerPAD HTQFPs.
PN and PZ are LQFPs.)		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP		 100-Pin
PZ
PZP		 80-Pin
PN
PFP
Instruction cycle – 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns 11.11 ns
Floating-Point Unit (FPU) Yes Yes Yes Yes Yes Yes Yes Yes
VCU Yes Yes No No Yes Yes No No
CLA 0 Yes No No No Yes No No No
6-Channel DMA 0 Yes Yes Yes Yes Yes Yes Yes Yes
On-chip Flash (16-bit word) – 128K 128K 128K 128K 64K 64K 64K 64K
On-chip SARAM (16-bit word) – 50K 50K 50K 34K 50K 50K 34K 26K
Code security for on-chip Flash, SARAM, and OTP blocks – Yes Yes Yes Yes Yes Yes Yes Yes
Boot ROM (32K × 16) – Yes Yes Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM
(16-bit word)		 – 1K 1K 1K 1K 1K 1K 1K 1K
ePWM channels 1 16 14 16 14 16 14 16 14 16 14 16 14 16 14 16 14
High-resolution ePWM Channels 1 8 8 8 8 8 8 8 8
eCAP inputs 0 3 3 3 3 3 3 3 3
HRCAP 0 4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1
eQEP modules 0 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
Watchdog timer – Yes Yes Yes Yes Yes Yes Yes Yes
12-Bit ADC MSPS 3 3.46 3.46 3.46 3.46 3.46 3.46 3.46 3.46
Conversion Time 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns 289 ns
Channels 16 12 16 12 16 12 16 12 16 12 16 12 16 12 16 12
Temperature Sensor Yes Yes Yes Yes Yes Yes Yes Yes
Dual Sample-and-Hold Yes Yes Yes Yes Yes Yes Yes Yes
32-Bit CPU timers – 3 3 3 3 3 3 3 3
Comparators with Integrated DACs 0 3 3 3 3 3 3 3 3
I2C 0 1 1 1 1 1 1 1 1
McBSP 1 1 1 1 1 1 1 1 1
eCAN 0 1 1 1 1 1 1 1 1
SPI 1 2 2 2 2 2 2 2 2
SCI 0 2 2 2 2 2 2 2 2
USB 0 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2) 1(2)
2-pin Oscillator 1 1 1 1 1 1 1 1
0-pin Oscillator 2 2 2 2 2 2 2 2
I/O pins (shared) GPIO – 54 40 54 40 54 40 54 40 54 40 54 40 54 40 54 40
AIO – 6 6 6 6 6 6 6 6
External interrupts – 3 3 3 3 3 3 3 3
Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Temperature options T: –40°C to 105°C – PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN PZ PN
S: –40°C to 125°C – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP
Q: –40°C to 125°C(5)(4) – PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP PZP PFP
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
(2) USB is present on TMS320F2806xU, TMS320F2806xM, and TMS320F2806xF devices.
(3) TMS320F2806xM devices are InstaSPIN-MOTION™-enabled MCUs. TMS320F2806xF devices are InstaSPIN-FOC™-enabled MCUs. For more information, see Section 8.3 for a list of InstaSPIN Technical Reference Manuals.
(4) The letter Q refers to AEC Q100 qualification for automotive applications.
(5) The Q temperature option is not available on the TMS320F2806xU devices.