SPRS698G November   2010  – May 2018 TMS320F28062 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28069

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
    5. 1.5 System Device Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT
      2. 5.5.1      Reducing Current Consumption
      3. 5.5.2      Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PFP PowerPAD Package
      2. 5.7.2 PZP PowerPAD Package
      3. 5.7.3 PN Package
      4. 5.7.4 PZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Emulator Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-5 2806x Clock Table and Nomenclature (90-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-8   XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-9   XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 90-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator (CLA)
      3. 6.1.3  Viterbi, Complex Math, CRC Unit (VCU)
      4. 6.1.4  Memory Bus (Harvard Bus Architecture)
      5. 6.1.5  Peripheral Bus
      6. 6.1.6  Real-Time JTAG and Analysis
      7. 6.1.7  Flash
      8. 6.1.8  M0, M1 SARAMs
      9. 6.1.9  L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs
      10. 6.1.10 Boot ROM
        1. 6.1.10.1 Emulation Boot
        2. 6.1.10.2 GetMode
        3. 6.1.10.3 Peripheral Pins Used by the Bootloader
      11. 6.1.11 Security
      12. 6.1.12 Peripheral Interrupt Expansion (PIE) Block
      13. 6.1.13 External Interrupts (XINT1 to XINT3)
      14. 6.1.14 Internal Zero Pin Oscillators, Oscillator, and PLL
      15. 6.1.15 Watchdog
      16. 6.1.16 Peripheral Clocking
      17. 6.1.17 Low-power Modes
      18. 6.1.18 Peripheral Frames 0, 1, 2, 3 (PFn)
      19. 6.1.19 General-Purpose Input/Output (GPIO) Multiplexer
      20. 6.1.20 32-Bit CPU-Timers (0, 1, 2)
      21. 6.1.21 Control Peripherals
      22. 6.1.22 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG, BOR, POR
      1. 6.5.1 On-chip VREG
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brownout Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 USB and HRCAP PLL Module (PLL2)
      5. 6.6.5 Loss of Input Clock (NMI Watchdog Function)
      6. 6.6.6 CPU-Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-20 External Interrupt Timing Requirements
          2. Table 6-21 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  CLA Overview
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter (ADC)
          1. 6.9.2.1.1 Features
          2. 6.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-26 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-27 ADC Electrical Characteristics
            2. Table 6-28 ADC Power Modes
            3. 6.9.2.1.3.1 Internal Temperature Sensor
              1. Table 6-29 Temperature Sensor Coefficient
            4. 6.9.2.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-30 ADC Power-Up Delays
            5. 6.9.2.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 ADC MUX
        3. 6.9.2.3 Comparator Block
          1. 6.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-32 Electrical Characteristics of the Comparator/DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface (SPI) Module
        1. 6.9.4.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-35 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-36 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-37 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-38 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface (SCI) Module
      6. 6.9.6  Multichannel Buffered Serial Port (McBSP) Module
        1. 6.9.6.1 McBSP Electrical Data/Timing
          1. 6.9.6.1.1 McBSP Transmit and Receive Timing
            1. Table 6-42 McBSP Timing Requirements
            2. Table 6-43 McBSP Switching Characteristics
          2. 6.9.6.1.2 McBSP as SPI Master or Slave Timing
            1. Table 6-44 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 6-45 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 6-46 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 6-47 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 6-48 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 6-49 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 6-50 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 6-51 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      7. 6.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 6.9.8  Inter-Integrated Circuit (I2C)
        1. 6.9.8.1 I2C Electrical Data/Timing
          1. Table 6-55 I2C Timing Requirements
          2. Table 6-56 I2C Switching Characteristics
      9. 6.9.9  Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)
        1. 6.9.9.1 ePWM Electrical Data/Timing
          1. Table 6-59 ePWM Timing Requirements
          2. Table 6-60 ePWM Switching Characteristics
        2. 6.9.9.2 Trip-Zone Input Timing
          1. Table 6-61 Trip-Zone Input Timing Requirements
      10. 6.9.10 High-Resolution PWM (HRPWM)
        1. 6.9.10.1 HRPWM Electrical Data/Timing
          1. Table 6-62 High-Resolution PWM Characteristics
      11. 6.9.11 Enhanced Capture Module (eCAP1)
        1. 6.9.11.1 eCAP Electrical Data/Timing
          1. Table 6-64 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-65 eCAP Switching Characteristics
      12. 6.9.12 High-Resolution Capture Modules (HRCAP1 to HRCAP4)
        1. 6.9.12.1 HRCAP Electrical Data/Timing
          1. Table 6-67 High-Resolution Capture (HRCAP) Timing Requirements
      13. 6.9.13 Enhanced Quadrature Encoder Modules (eQEP1, eQEP2)
        1. 6.9.13.1 eQEP Electrical Data/Timing
          1. Table 6-69 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. Table 6-70 eQEP Switching Characteristics
      14. 6.9.14 JTAG Port
      15. 6.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.15.1 GPIO Electrical Data/Timing
          1. 6.9.15.1.1 GPIO Output Timing
            1. Table 6-76 General-Purpose Output Switching Characteristics
          2. 6.9.15.1.2 GPIO Input Timing
            1. Table 6-77 General-Purpose Input Timing Requirements
          3. 6.9.15.1.3 Sampling Window Width for Input Signals
          4. 6.9.15.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-78 IDLE Mode Timing Requirements
            2. Table 6-79 IDLE Mode Switching Characteristics
            3. Table 6-80 STANDBY Mode Timing Requirements
            4. Table 6-81 STANDBY Mode Switching Characteristics
            5. Table 6-82 HALT Mode Timing Requirements
            6. Table 6-83 HALT Mode Switching Characteristics
      16. 6.9.16 Universal Serial Bus (USB)
        1. 6.9.16.1 USB Electrical Data/Timing
          1. Table 6-84 USB Input Ports DP and DM Timing Requirements
          2. Table 6-85 USB Output Ports DP and DM Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)

The devices contain up to eight enhanced PWM (ePWM) modules. Figure 6-48 shows a block diagram of multiple ePWM modules. Figure 6-49 shows the signal interconnections with the ePWM.

Table 6-57 and Table 6-58 show the complete ePWM register set per module.

TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 epwm_prs698.gif
This signal exists only on devices with an eQEP1 module.
Figure 6-48 ePWM

Table 6-57 ePWM1–ePWM4 Control and Status Registers

NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (×16)/
#SHADOW
DESCRIPTION
TBCTL 0x6800 0x6840 0x6880 0x68C0 1/0 Time Base Control Register
TBSTS 0x6801 0x6841 0x6881 0x68C1 1/0 Time Base Status Register
TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1/0 Time Base Phase HRPWM Register
TBPHS 0x6803 0x6843 0x6883 0x68C3 1/0 Time Base Phase Register
TBCTR 0x6804 0x6844 0x6884 0x68C4 1/0 Time Base Counter Register
TBPRD 0x6805 0x6845 0x6885 0x68C5 1/1 Time Base Period Register Set
TBPRDHR 0x6806 0x6846 0x6886 0x68C6 1/1 Time Base Period High-Resolution Register(1)
CMPCTL 0x6807 0x6847 0x6887 0x68C7 1/0 Counter Compare Control Register
CMPAHR 0x6808 0x6848 0x6888 0x68C8 1/1 Time Base Compare A HRPWM Register
CMPA 0x6809 0x6849 0x6889 0x68C9 1/1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 1/1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 1/0 Action Qualifier Control Register For Output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 1/0 Action Qualifier Control Register For Output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 1/0 Action Qualifier Software Force Register
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1/1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 1/1 Dead-Band Generator Control Register
DBRED 0x6810 0x6850 0x6890 0x68D0 1/0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6811 0x6851 0x6891 0x68D1 1/0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6812 0x6852 0x6892 0x68D2 1/0 Trip Zone Select Register(1)
TZDCSEL 0x6813 0x6853 0x6893 0x68D3 1/0 Trip Zone Digital Compare Register
TZCTL 0x6814 0x6854 0x6894 0x68D4 1/0 Trip Zone Control Register(1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 1/0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 1/0 Trip Zone Flag Register (1)
TZCLR 0x6817 0x6857 0x6897 0x68D7 1/0 Trip Zone Clear Register(1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 1/0 Trip Zone Force Register(1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 1/0 Event Trigger Selection Register
ETPS 0x681A 0x685A 0x689A 0x68DA 1/0 Event Trigger Prescale Register
ETFLG 0x681B 0x685B 0x689B 0x68DB 1/0 Event Trigger Flag Register
ETCLR 0x681C 0x685C 0x689C 0x68DC 1/0 Event Trigger Clear Register
ETFRC 0x681D 0x685D 0x689D 0x68DD 1/0 Event Trigger Force Register
PCCTL 0x681E 0x685E 0x689E 0x68DE 1/0 PWM Chopper Control Register
HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1/0 HRPWM Configuration Register(1)
HRMSTEP 0x6826 - - - 1/0 HRPWM MEP Step Register
HRPCTL 0x6828 0x6868 0x68A8 0x68E8 1/0 High-resolution Period Control Register(1)
TBPRDHRM 0x682A 0x686A 0x68AA 0x68EA 1/W(2) Time Base Period HRPWM Register Mirror
TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1/W(2) Time Base Period Register Mirror
CMPAHRM 0x682C 0x686C 0x68AC 0x68EC 1/W(2) Compare A HRPWM Register Mirror
CMPAM 0x682D 0x686D 0x68AD 0x68ED 1/W(2) Compare A Register Mirror
DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1/0 Digital Compare Trip Select Register (1)
DCACTL 0x6831 0x6871 0x68B1 0x68F1 1/0 Digital Compare A Control Register(1)
DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1/0 Digital Compare B Control Register(1)
DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1/0 Digital Compare Filter Control Register(1)
DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1/0 Digital Compare Capture Control Register(1)
DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1/1 Digital Compare Filter Offset Register
DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1/0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1/0 Digital Compare Filter Window Register
DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1/0 Digital Compare Filter Window Counter Register
DCCAP 0x6839 0x6879 0x68B9 0x68F9 1/1 Digital Compare Counter Capture Register
Registers that are EALLOW protected.
W = Write to shadow register

Table 6-58 ePWM5–ePWM8 Control and Status Registers

NAME ePWM5 ePWM6 ePWM7 ePWM8 SIZE (×16)/
#SHADOW
DESCRIPTION
TBCTL 0x6900 0x6940 0x6980 0x69C0 1/0 Time Base Control Register
TBSTS 0x6901 0x6941 0x6981 0x69C1 1/0 Time Base Status Register
TBPHSHR 0x6902 0x6942 0x6982 0x69C2 1/0 Time Base Phase HRPWM Register
TBPHS 0x6903 0x6943 0x6983 0x69C3 1/0 Time Base Phase Register
TBCTR 0x6904 0x6944 0x6984 0x69C4 1/0 Time Base Counter Register
TBPRD 0x6905 0x6945 0x6985 0x69C5 1/1 Time Base Period Register Set
TBPRDHR 0x6906 0x6946 0x6986 0x69C6 1/1 Time Base Period High-Resolution Register(1)
CMPCTL 0x6907 0x6947 0x6987 0x69C7 1/0 Counter Compare Control Register
CMPAHR 0x6908 0x6948 0x6988 0x69C8 1/1 Time Base Compare A HRPWM Register
CMPA 0x6909 0x6949 0x6989 0x69C9 1/1 Counter Compare A Register Set
CMPB 0x690A 0x694A 0x698A 0x69CA 1/1 Counter Compare B Register Set
AQCTLA 0x690B 0x694B 0x698B 0x69CB 1/0 Action Qualifier Control Register For Output A
AQCTLB 0x690C 0x694C 0x698C 0x69CC 1/0 Action Qualifier Control Register For Output B
AQSFRC 0x690D 0x694D 0x698D 0x69CD 1/0 Action Qualifier Software Force Register
AQCSFRC 0x690E 0x694E 0x698E 0x69CE 1/1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x690F 0x694F 0x698F 0x69CF 1/1 Dead-Band Generator Control Register
DBRED 0x6910 0x6950 0x6990 0x69D0 1/0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6911 0x6951 0x6991 0x69D1 1/0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6912 0x6952 0x6992 0x69D2 1/0 Trip Zone Select Register(1)
TZDCSEL 0x6913 0x6953 0x6993 0x69D3 1/0 Trip Zone Digital Compare Register
TZCTL 0x6914 0x6954 0x6994 0x69D4 1/0 Trip Zone Control Register(1)
TZEINT 0x6915 0x6955 0x6995 0x69D5 1/0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6916 0x6956 0x6996 0x69D6 1/0 Trip Zone Flag Register (1)
TZCLR 0x6917 0x6957 0x6997 0x69D7 1/0 Trip Zone Clear Register(1)
TZFRC 0x6918 0x6958 0x6998 0x69D8 1/0 Trip Zone Force Register(1)
ETSEL 0x6919 0x6959 0x6999 0x69D9 1/0 Event Trigger Selection Register
ETPS 0x691A 0x695A 0x699A 0x69DA 1/0 Event Trigger Prescale Register
ETFLG 0x691B 0x695B 0x699B 0x69DB 1/0 Event Trigger Flag Register
ETCLR 0x691C 0x695C 0x699C 0x69DC 1/0 Event Trigger Clear Register
ETFRC 0x691D 0x695D 0x699D 0x69DD 1/0 Event Trigger Force Register
PCCTL 0x691E 0x695E 0x699E 0x69DE 1/0 PWM Chopper Control Register
HRCNFG 0x6920 0x6960 0x69A0 0x69E0 1/0 HRPWM Configuration Register(1)
HRMSTEP - - - - 1/0 HRPWM MEP Step Register
HRPCTL 0x6928 0x6968 0x69A8 0x69E8 1/0 High-resolution Period Control Register(1)
TBPRDHRM 0x692A 0x696A 0x69AA 0x69EA 1/W(2) Time Base Period HRPWM Register Mirror
TBPRDM 0x692B 0x696B 0x69AB 0x69EB 1/W(2) Time Base Period Register Mirror
CMPAHRM 0x692C 0x696C 0x69AC 0x69EC 1/W(2) Compare A HRPWM Register Mirror
CMPAM 0x692D 0x696D 0x69AD 0x69ED 1/W(2) Compare A Register Mirror
DCTRIPSEL 0x6930 0x6970 0x69B0 0x69F0 1/0 Digital Compare Trip Select Register (1)
DCACTL 0x6931 0x6971 0x69B1 0x69F1 1/0 Digital Compare A Control Register(1)
DCBCTL 0x6932 0x6972 0x69B2 0x69F2 1/0 Digital Compare B Control Register(1)
DCFCTL 0x6933 0x6973 0x69B3 0x69F3 1/0 Digital Compare Filter Control Register(1)
DCCAPCT 0x6934 0x6974 0x69B4 0x69F4 1/0 Digital Compare Capture Control Register(1)
DCFOFFSET 0x6935 0x6975 0x69B5 0x69F5 1/1 Digital Compare Filter Offset Register
DCFOFFSETCNT 0x6936 0x6976 0x69B6 0x69F6 1/0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6937 0x6977 0x69B7 0x69F7 1/0 Digital Compare Filter Window Register
DCFWINDOWCNT 0x6938 0x6978 0x69B8 0x69F8 1/0 Digital Compare Filter Window Counter Register
DCCAP 0x6939 0x6979 0x69B9 0x69F9 1/1 Digital Compare Counter Capture Register
Registers that are EALLOW protected.
W = Write to shadow register
TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 fbd_hires_prs698.gif
These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals.
This signal exists only on devices with an eQEP1 module.
Figure 6-49 ePWM Submodules Showing Critical Internal Signal Interconnections