SPRS698G November   2010  – May 2018 TMS320F28062 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28069

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
    5. 1.5 System Device Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT
      2. 5.5.1      Reducing Current Consumption
      3. 5.5.2      Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PFP PowerPAD Package
      2. 5.7.2 PZP PowerPAD Package
      3. 5.7.3 PN Package
      4. 5.7.4 PZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Emulator Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-5 2806x Clock Table and Nomenclature (90-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-8   XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-9   XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 90-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator (CLA)
      3. 6.1.3  Viterbi, Complex Math, CRC Unit (VCU)
      4. 6.1.4  Memory Bus (Harvard Bus Architecture)
      5. 6.1.5  Peripheral Bus
      6. 6.1.6  Real-Time JTAG and Analysis
      7. 6.1.7  Flash
      8. 6.1.8  M0, M1 SARAMs
      9. 6.1.9  L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs
      10. 6.1.10 Boot ROM
        1. 6.1.10.1 Emulation Boot
        2. 6.1.10.2 GetMode
        3. 6.1.10.3 Peripheral Pins Used by the Bootloader
      11. 6.1.11 Security
      12. 6.1.12 Peripheral Interrupt Expansion (PIE) Block
      13. 6.1.13 External Interrupts (XINT1 to XINT3)
      14. 6.1.14 Internal Zero Pin Oscillators, Oscillator, and PLL
      15. 6.1.15 Watchdog
      16. 6.1.16 Peripheral Clocking
      17. 6.1.17 Low-power Modes
      18. 6.1.18 Peripheral Frames 0, 1, 2, 3 (PFn)
      19. 6.1.19 General-Purpose Input/Output (GPIO) Multiplexer
      20. 6.1.20 32-Bit CPU-Timers (0, 1, 2)
      21. 6.1.21 Control Peripherals
      22. 6.1.22 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG, BOR, POR
      1. 6.5.1 On-chip VREG
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brownout Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 USB and HRCAP PLL Module (PLL2)
      5. 6.6.5 Loss of Input Clock (NMI Watchdog Function)
      6. 6.6.6 CPU-Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-20 External Interrupt Timing Requirements
          2. Table 6-21 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  CLA Overview
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter (ADC)
          1. 6.9.2.1.1 Features
          2. 6.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-26 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-27 ADC Electrical Characteristics
            2. Table 6-28 ADC Power Modes
            3. 6.9.2.1.3.1 Internal Temperature Sensor
              1. Table 6-29 Temperature Sensor Coefficient
            4. 6.9.2.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-30 ADC Power-Up Delays
            5. 6.9.2.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 ADC MUX
        3. 6.9.2.3 Comparator Block
          1. 6.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-32 Electrical Characteristics of the Comparator/DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface (SPI) Module
        1. 6.9.4.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-35 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-36 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-37 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-38 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface (SCI) Module
      6. 6.9.6  Multichannel Buffered Serial Port (McBSP) Module
        1. 6.9.6.1 McBSP Electrical Data/Timing
          1. 6.9.6.1.1 McBSP Transmit and Receive Timing
            1. Table 6-42 McBSP Timing Requirements
            2. Table 6-43 McBSP Switching Characteristics
          2. 6.9.6.1.2 McBSP as SPI Master or Slave Timing
            1. Table 6-44 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 6-45 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 6-46 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 6-47 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 6-48 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 6-49 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 6-50 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 6-51 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      7. 6.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 6.9.8  Inter-Integrated Circuit (I2C)
        1. 6.9.8.1 I2C Electrical Data/Timing
          1. Table 6-55 I2C Timing Requirements
          2. Table 6-56 I2C Switching Characteristics
      9. 6.9.9  Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)
        1. 6.9.9.1 ePWM Electrical Data/Timing
          1. Table 6-59 ePWM Timing Requirements
          2. Table 6-60 ePWM Switching Characteristics
        2. 6.9.9.2 Trip-Zone Input Timing
          1. Table 6-61 Trip-Zone Input Timing Requirements
      10. 6.9.10 High-Resolution PWM (HRPWM)
        1. 6.9.10.1 HRPWM Electrical Data/Timing
          1. Table 6-62 High-Resolution PWM Characteristics
      11. 6.9.11 Enhanced Capture Module (eCAP1)
        1. 6.9.11.1 eCAP Electrical Data/Timing
          1. Table 6-64 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-65 eCAP Switching Characteristics
      12. 6.9.12 High-Resolution Capture Modules (HRCAP1 to HRCAP4)
        1. 6.9.12.1 HRCAP Electrical Data/Timing
          1. Table 6-67 High-Resolution Capture (HRCAP) Timing Requirements
      13. 6.9.13 Enhanced Quadrature Encoder Modules (eQEP1, eQEP2)
        1. 6.9.13.1 eQEP Electrical Data/Timing
          1. Table 6-69 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. Table 6-70 eQEP Switching Characteristics
      14. 6.9.14 JTAG Port
      15. 6.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.15.1 GPIO Electrical Data/Timing
          1. 6.9.15.1.1 GPIO Output Timing
            1. Table 6-76 General-Purpose Output Switching Characteristics
          2. 6.9.15.1.2 GPIO Input Timing
            1. Table 6-77 General-Purpose Input Timing Requirements
          3. 6.9.15.1.3 Sampling Window Width for Input Signals
          4. 6.9.15.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-78 IDLE Mode Timing Requirements
            2. Table 6-79 IDLE Mode Switching Characteristics
            3. Table 6-80 STANDBY Mode Timing Requirements
            4. Table 6-81 STANDBY Mode Switching Characteristics
            5. Table 6-82 HALT Mode Timing Requirements
            6. Table 6-83 HALT Mode Switching Characteristics
      16. 6.9.16 Universal Serial Bus (USB)
        1. 6.9.16.1 USB Electrical Data/Timing
          1. Table 6-84 USB Input Ports DP and DM Timing Requirements
          2. Table 6-85 USB Output Ports DP and DM Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

General-Purpose Input/Output (GPIO) MUX

The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability.

The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-71 shows the GPIO register mapping.

Table 6-71 GPIO Registers

NAME ADDRESS SIZE (×16) DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)
GPAPUD 0x6F8C 2 GPIO A Pullup Disable Register (GPIO0 to 31)
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 44)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 44)
GPBQSEL2 0x6F94 2 GPIO B Qualifier Select 2 Register
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 44)
GPBMUX2 0x6F98 2 GPIO B MUX 2 Register (GPIO50 to 58)
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 44)
GPBPUD 0x6F9C 2 GPIO B Pullup Disable Register (GPIO32 to 44)
AIOMUX1 0x6FB6 2 Analog, I/O mux 1 register (AIO0 to AIO15)
AIODIR 0x6FBA 2 Analog, I/O Direction Register (AIO0 to AIO15)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 44)
GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 44)
GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 44)
GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 44)
AIODAT 0x6FD8 2 Analog I/O Data Register (AIO0 to AIO15)
AIOSET 0x6FDA 2 Analog I/O Data Set Register (AIO0 to AIO15)
AIOCLEAR 0x6FDC 2 Analog I/O Data Clear Register (AIO0 to AIO15)
AIOTOGGLE 0x6FDE 2 Analog I/O Data Toggle Register (AIO0 to AIO15)
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL 0x6FE2 1 XINT3 GPIO Input Select Register (GPIO0 to 31)
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)

NOTE

There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and GPxQSELn registers occurs to when the action is valid.

Table 6-72 GPIOA MUX(1)(2)

DEFAULT AT RESET
PRIMARY I/O FUNCTION
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
GPAMUX1 REGISTER BITS (GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11)
1-0 GPIO0 EPWM1A (O) Reserved Reserved
3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O)
5-4 GPIO2 EPWM2A (O) Reserved Reserved
7-6 GPIO3 EPWM2B (O) SPISOMIA (I/O) COMP2OUT (O)
9-8 GPIO4 EPWM3A (O) Reserved Reserved
11-10 GPIO5 EPWM3B (O) SPISIMOA (I/O) ECAP1 (I/O)
13-12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
15-14 GPIO7 EPWM4B (O) SCIRXDA (I) ECAP2 (I/O)
17-16 GPIO8 EPWM5A (O) Reserved ADCSOCAO (O)
19-18 GPIO9 EPWM5B (O) SCITXDB (O) ECAP3 (I/O)
21-20 GPIO10 EPWM6A (O) Reserved ADCSOCBO (O)
23-22 GPIO11 EPWM6B (O) SCIRXDB (I) ECAP1 (I/O)
25-24 GPIO12 TZ1 (I) SCITXDA (O) SPISIMOB (I/O)
27-26 GPIO13 TZ2 (I) Reserved SPISOMIB (I/O)
29-28 GPIO14 TZ3 (I) SCITXDB (O) SPICLKB (I/O)
31-30 GPIO15 ECAP2 (I/O) SCIRXDB (I) SPISTEB (I/O)
GPAMUX2 REGISTER BITS (GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11)
1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I)
3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I)
5-4 GPIO18 SPICLKA (I/O) SCITXDB (O) XCLKOUT (O)
7-6 GPIO19/XCLKIN SPISTEA (I/O) SCIRXDB (I) ECAP1 (I/O)
9-8 GPIO20 EQEP1A (I) MDXA (O) COMP1OUT (O)
11-10 GPIO21 EQEP1B (I) MDRA (I) COMP2OUT (O)
13-12 GPIO22 EQEP1S (I/O) MCLKXA (I/O) SCITXDB (O)
15-14 GPIO23 EQEP1I (I/O) MFSXA (I/O) SCIRXDB (I)
17-16 GPIO24 ECAP1 (I/O) EQEP2A(3) (I) SPISIMOB (I/O)
19-18 GPIO25 ECAP2 (I/O) EQEP2B(3) (I) SPISOMIB (I/O)
21-20 GPIO26(4) ECAP3 (I/O) EQEP2I(3) (I/O) SPICLKB (I/O)
23-22 GPIO27(4) HRCAP2 (I) EQEP2S(3) (I/O) SPISTEB (I/O)
25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) TZ2 (I)
27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I)
29-28 GPIO30 CANRXA (I) EQEP2I(3) (I/O) EPWM7A (O)
31-30 GPIO31 CANTXA (O) EQEP2S(3) (I/O) EPWM8A (O)
The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
I = Input, O = Output, OD = Open Drain
The eQEP2 peripheral is not available on the 80-pin PN or PFP package.
To enable the USB functionality on GPIO26 (USB0DP, positive differential half of the USB signal) and GPIO27 (USB0DM, negative differential half of the USB signal), set the USBIOEN bit in the GPACTRL2 register. Depending on your USB application, additional pins may be required to maintain compliance with the USB 2.0 Specification. For more information, see the Universal Serial Bus (USB) Controller chapter of the TMS320x2806x Technical Reference Manual.

Table 6-73 GPIOB MUX(1)(2)

DEFAULT AT RESET
PRIMARY I/O FUNCTION
PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 PERIPHERAL SELECTION 3
GPBMUX1 REGISTER BITS (GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11)
1-0 GPIO32 SDAA (I/OD) EPWMSYNCI (I) ADCSOCAO (O)
3-2 GPIO33 SCLA (I/OD) EPWMSYNCO (O) ADCSOCBO (O)
5-4 GPIO34 COMP2OUT (O) Reserved COMP3OUT (O)
7-6 GPIO35 (TDI) Reserved Reserved Reserved
9-8 GPIO36 (TMS) Reserved Reserved Reserved
11-10 GPIO37 (TDO) Reserved Reserved Reserved
13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved
15-14 GPIO39 Reserved Reserved Reserved
17-16 GPIO40(3) EPWM7A (O) SCITXDB (O) Reserved
19-18 GPIO41(3) EPWM7B (O) SCIRXDB (I) Reserved
21-20 GPIO42(3) EPWM8A (O) TZ1 (I) COMP1OUT (O)
23-22 GPIO43(3) EPWM8B (O) TZ2 (I) COMP2OUT (O)
25-24 GPIO44(3) MFSRA (I/O) SCIRXDB (I) EPWM7B (O)
27-26 Reserved Reserved Reserved Reserved
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
GPBMUX2 REGISTER BITS (GPBMUX2 BITS = 00) (GPBMUX2 BITS = 01) (GPBMUX2 BITS = 10) (GPBMUX2 BITS = 11)
1-0 Reserved Reserved Reserved Reserved
3-2 Reserved Reserved Reserved Reserved
5-4 GPIO50(3) EQEP1A (I) MDXA (O) TZ1 (I)
7-6 GPIO51(3) EQEP1B (I) MDRA (I) TZ2 (I)
9-8 GPIO52(3) EQEP1S (I/O) MCLKXA (I/O) TZ3 (I)
11-10 GPIO53(3) EQEP1I (I/O) MFSXA (I/O) Reserved
13-12 GPIO54(3) SPISIMOA (I/O) EQEP2A (I) HRCAP1 (I)
15-14 GPIO55(3) SPISOMIA (I/O) EQEP2B (I) HRCAP2 (I)
17-16 GPIO56(3) SPICLKA (I/O) EQEP2I (I/O) HRCAP3 (I)
19-18 GPIO57(3) SPISTEA (I/O) EQEP2S (I/O) HRCAP4 (I)
21-20 GPIO58(3) MCLKRA (I/O) SCITXDB (O) EPWM7A (O)
23-22 Reserved Reserved Reserved Reserved
25-24 Reserved Reserved Reserved Reserved
27-26 Reserved Reserved Reserved Reserved
29-28 Reserved Reserved Reserved Reserved
31-30 Reserved Reserved Reserved Reserved
The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
I = Input, O = Output, OD = Open Drain
This pin is not available in the 80-pin PN or PFP package.

Table 6-74 Analog MUX for 100-Pin PZ and 100-Pin PZP Packages(1)

DEFAULT AT RESET
AIOx AND PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 AND PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I) ADCINA0 (I)
3-2 ADCINA1 (I) ADCINA1 (I)
5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I)
7-6 ADCINA3 (I) ADCINA3 (I)
9-8 AIO4 (I/O) ADCINA4 (I), COMP2A (I)
11-10 ADCINA5 (I) ADCINA5 (I)
13-12 AIO6 (I/O) ADCINA6 (I), COMP3A (I)
15-14 ADCINA7 (I) ADCINA7 (I)
17-16 ADCINB0 (I) ADCINB0 (I)
19-18 ADCINB1 (I) ADCINB1 (I)
21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I)
23-22 ADCINB3 (I) ADCINB3 (I)
25-24 AIO12 (I/O) ADCINB4 (I), COMP2B (I)
27-26 ADCINB5 (I) ADCINB5 (I)
29-28 AIO14 (I/O) ADCINB6 (I), COMP3B (I)
31-30 ADCINB7 (I) ADCINB7 (I)
I = Input, O = Output

Table 6-75 Analog MUX for 80-Pin PN and 80-Pin PFP Packages(1)

DEFAULT AT RESET
AIOx AND PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 AND PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I), VREFHI (I) ADCINA0 (I), VREFHI (I)
3-2 ADCINA1 (I) ADCINA1 (I)
5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I)
7-6
9-8 AIO4 (I/O) ADCINA4 (I), COMP2A (I)
11-10 ADCINA5 (I) ADCINA5 (I)
13-12 AIO6 (I/O) ADCINA6 (I), COMP3A (I)
15-14
17-16 ADCINB0 (I) ADCINB0 (I)
19-18 ADCINB1 (I) ADCINB1 (I)
21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I)
23-22
25-24 AIO12 (I/O) ADCINB4 (I), COMP2B (I)
27-26 ADCINB5 (I) ADCINB5 (I)
29-28 AIO14 (I/O) ADCINB6 (I), COMP3B (I)
31-30
I = Input, O = Output

The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from four choices:

  • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
  • Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change.
  • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. The sampling period specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
  • No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral).

Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.

TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063 TMS320F28062 fbd_gpiomux_prs698.gif
x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected.
GPxDAT latch/read are accessed at the same memory location.
This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the Systems Control and Interrupts chapter of the TMS320x2806x Technical Reference Manual for pin-specific variations.
Figure 6-55 GPIO Multiplexing