SPRS698H November 2010 – March 2020 TMS320F28062 , TMS320F28062F , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069F , TMS320F28069M
In addition to the main system PLL, these devices also contain a second PLL (PLL2) which can be used to clock the USB and HRCAP peripherals. The PLL supports multipliers of 1 to 15 and has a fixed divide-by-two on its output.
PLL2 may be clocked from the following three sources by modifying the PLL2CLKSRCSEL bits appropriately in the PLL2CTL register:
For proper operation of the USB module, PLL2 should be configured to generate a 120-MHz clock. This will be divided by two to yield the desired 60 MHz for the USB peripheral.
HRCAP supports a maximum clock input frequency of 120 MHz.