SPRS698H November 2010 – March 2020 TMS320F28062 , TMS320F28062F , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069F , TMS320F28069M
Table 6-16 summarizes the various modes.
|IDLE||00||On||On||On||XRS, CPU-watchdog interrupt, any enabled interrupt|
(CPU-watchdog still running)
|Off||Off||XRS, CPU-watchdog interrupt, GPIO Port A signal, debugger(2)|
(on-chip crystal oscillator and PLL turned off, zero-pin oscillator and CPU-watchdog state dependent on user code.)
|Off||Off||XRS, GPIO Port A signal, debugger(2), CPU-watchdog|
The various low-power modes operate as follows:
|IDLE Mode:||This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.|
|STANDBY Mode:||Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signals will wake the device in the GPIOLPMSEL register. The selected signals are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register.|
|HALT Mode:||CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The user selects the signal in the GPIOLPMSEL register.|
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the Systems Control and Interrupts chapter of the TMS320x2806x Technical Reference Manual for more details.